Method and apparatus for constructing a dynamic adaptive neural network array (danna)

ABSTRACT

A circuit element of a multi-dimensional dynamic adaptive neural network array (DANNA) may comprise a neuron/synapse select input functional to select the circuit element to function as one of a neuron and a synapse. In one embodiment of a DANNA array of such circuit elements, (wherein a circuit element or component thereof may be analog or digital), a destination neuron may be connected to a first neuron by a first synapse in one dimension, a second destination neuron may be connected to the first neuron by a second synapse in a second dimension and, optionally, a third destination neuron may be connected to the first neuron by a third synapse. The DANNA may thus form multiple levels of neuron and synapse circuit elements. In one embodiment, multiples of eight inputs may be selectively received by the circuit element selectively functioning as one of a neuron and a synapse. The dynamic adaptive neural network array (DANNA) may comprise a special purpose processor for performing one of a control, anomaly detection and classification application and may comprise a first structure connected to a neuroscience-inspired dynamic artificial neural network (NIDA), comprise substructures thereof or be combined with other neural networks.

The present patent application claims the benefit of and right of priority to U.S. Provisional Patent Applications, Ser. No. 61/891,621, filed Oct. 16, 2013; Ser. No. 61/934,052, filed Jan. 31, 2014; Ser. No. 61/946,179 filed Feb. 28, 2014; Ser. No. 61/951,690 filed Mar. 12, 2014, Ser. No. 62/001,951, filed May 22, 2014, and Ser. No. 62/024,081, filed Jul. 14, 2015, all six U.S. provisional patent applications incorporated by reference herein as to their entire contents and is related by subject matter to U.S. patent application Ser. No. 14/513,280 (Attorney Docket No. 204842.031) filed Oct. 14, 2014, entitled “Method and Apparatus for Constructing a Neuroscience-Inspired Artificial Neural Network” of J. Douglas Birdwell and Catherine Schuman, to U.S. patent application Ser. No. 14/513,334 (Attorney Docket No. 204842.033) filed Oct. 14, 2014, entitled “Method and Apparatus for Providing Random Selection and Long-Term Potentiation and Depression in an Artificial Network” of J. Douglas Birdwell, Mark E. Dean and Catherine Schuman, to U.S. patent application Ser. No. 14/513,388 (Attorney Docket No. 204842.034) filed Oct. 14, 2014, entitled “Method and Apparatus for Constructing, Using and Reusing Components and Structures of an Artificial Neural Network” of J. Douglas Birdwell, Mark E. Dean and Catherine Schuman, to U.S. patent application Ser. No. 14/513,447 (Attorney Docket No. 204842.035) filed Oct. 14, 2014, entitled “Method and Apparatus for Providing Real-Time Monitoring of an Artificial Neural Network” of J. Douglas Birdwell, Mark E. Dean and Catherine Schuman and to U.S. patent application Ser. No. 14/513,497 (Attorney Docket No. 204842.036) filed Oct. 14, 2014, entitled “Method and Apparatus for Constructing a Neuroscience-Inspired Artificial Neural Network with Visualization of Neural Pathways” of J. Douglas Birdwell, Mark E. Dean, Margaret Drouhard and Catherine Schuman, all five patent applications incorporated by reference as to their entire contents.

TECHNICAL FIELD

The technical field relates to a method and apparatus for constructing a neuroscience-inspired artificial neural network embodied in a dynamic adaptive neural network array (DANNA) and, in particular, to the application of a conventional von Neumann architecture to support a neuroscience-inspired artificial neural network dynamic architecture in software and a DANNA from primary neuron and synapse elements of one of a programmable logic array, application specific integrated circuit, VLSI component or other component for solving problems in the control, anomaly detection and classification arts.

BACKGROUND AND RELATED ARTS

Biological neural networks are known to have many desirable characteristics. For example, they are able to perform complex, nonlinear tasks using large numbers of relatively simple building blocks. Biological neural networks are robust, able to extrapolate information from a specific setting to apply to a more general setting, and adaptable to change. For these reasons and many others, it has been a goal of the machine learning community to produce networks with similar capabilities to biological central nervous systems, brains and, in particular to the human brain.

In order to appreciate the neuroscience-inspired artificial neural network of the present invention, a brief introduction to the neural components, by example, of the human brain and the larger components of the human brain itself is provided. Biological neurons are the nerve cells present in the brain. The human brain consists of about 10¹¹ neurons, each of which operates in parallel with the others. A typical biological neuron is shown in FIG. 1. A process in neuroscience usually refers to a physical feature. The various processes of the neuron are called neurites; henceforth, the term neurite will be used rather than process to avoid confusion with the computer science notion of process. The neuron receives information through neurites called dendrites 110, which also communicate the information to the neuron's cell body 120. The cell body 120 has a nucleus 130. The neurite that transmits information out of the neuron to other targets is called the axon 140 having axon terminals 190. A myelin sheath 160 comprises a Schwann cell 170. Signals between neurons are usually transferred across synapses, although direct connections that allow ion exchange have been observed. Typically, the communication is done chemically via neurotransmitters.

Dendrites 110 are usually shorter than axons 140 and arise from the cell body 120 of the neuron. They generally branch off into dendritic spines, which receive information from axons from other neurons. The dendritic spines are typically where the communication between neurons across synapses and from axons takes place, although sometimes communication is direct from cell body to cell body, or between dendrites.

Although information is transmitted from an axon 140 to a dendrite 110 in a typical synapse, there are also synapses between two axons, two dendrites, and synapses and from axons in which information travels from dendrite 110 to axon 140. Because of these differences, connections between neurons in the artificial neural networks defined herein will all be referred to only as synapses, with no distinction between dendrites and axons. The synapses as known in biological systems are uni-directional in that information travels from one neuron to another via a synapse connection, but not in the opposite direction along that synapse.

There are two ways for synaptic transmission to take place in the brain: electrical transmission and chemical transmission. Electrical transmission occurs when the current generated by one neuron spreads to another neuron on a pathway of low electrical resistance. Electrical synapses are relatively rare in the mammalian brain; evidence suggests that they occur in regions where the activities of neighboring neurons need to be highly synchronized. In chemical transmissions, neurotransmitters are transmitted from one neuron to another.

A neurotransmitter is a chemical substance that is typically synthesized in a neuron and is released at a synapse following depolarization of at least a portion of the neuron's cell membrane (typically near the synapse). The neurotransmitter then binds to receptors at a postsynaptic cell and/or postsynaptic terminal to elicit a response. This response may excite or inhibit the neuron, meaning neurotransmitters play a major role in the way the brain operates. Some of the known neurotransmitters are acetylcholine, glutamate, GABA, glycine, dopamine, norepinephrine, serotonin and histamine.

Neurotransmitters are released according to action potentials in the neuron. An action potential is a fluctuation in the membrane potential of the neuron, which is the voltage difference across the cell membrane caused by differences in ion concentrations between the outside and inside of the neuron. Neurons have a particular membrane potential in which they are at rest. Typically, a neuron is “at rest” when the potential inside the neuron's cell wall is approximately −70 mV compared to the outside of the neuron. When positively charged ions flow out of the cell, the membrane potential becomes more negative, while positive ionic current flowing into the cell changes the membrane potential to a less negative or positive value. Negative ions have an opposite effect. Each neuron has an associated threshold level. If the membrane potential rises above this threshold level, the neuron generates an action potential. The generation of the action potential is called a “firing” of the neuron.

The generation of an action potential relies not only on the threshold of the neuron but also on the recent firing history. Each neuron has an associated refractory period. For a short period of time after a neuron has fired, it is highly unlikely that that neuron will fire again. This period is called the absolute refractory period. For a slightly longer period of time after the absolute refractory period, it is difficult, but more likely, for the neuron to fire again. This period is called the relative refractory period.

In the central nervous system, multiple types of cells provide myelin sheaths 160 along axons 140. Myelin is a fat that provides an insulating layer for the axon 140. The thickness of the myelin sheath 160 controls the propagation delay of signals along the axon 140. Myelin sheaths 160 are separated along the axon by nodes of Ranvier 150. The action potential traveling along the axon is regenerated at each of the nodes of Ranvier. Having described a typical neuron, the parts of the human brain will now be discussed with reference to FIG. 2.

The basal ganglia (corpus striatum) 210 is one of the most important layers of the brain 200 for emotion processing and generation; it is also known as the reptilian brain. The basal ganglia connects the cerebral cortex and the cerebellum. The basal ganglia 210 is the portion of the brain that contains innate behavioral knowledge, including motor functions and primal emotions such as fear, anger, and sexuality. It is also responsible for motor integration in the cerebral cortex, i.e. it helps regulate movement. The next layer of the brain known as the limbic system or the visceral brain, is where many of the various social emotions are processed. It processes most affective knowledge, generating more sophisticated emotional responses. The limbic system also appears to mediate or control memory processes. Both the amygdala 220 and the hippocampus 230 are part of the limbic system. The hippocampus 230 plays an important role in memory formation in the brain, particularly short term memory (memory of new information and recent events). The amygdala 220 is important for learning associations between stimuli and emotional value (emotional responses and aggressive behavior). For example, the amygdala may associate fear with a stimulus that causes pain.

The neocortex 240 is the structure in the brain that is more evolved in human brains than in other mammal brains. The neocortex 240 is responsible for associating a diversity of sensations and innate ideas, such as a sense of causality and spatial referencing, into perception, concepts and attributions. This is the portion of the brain that contains what we think of as the rational mind and the imagination and the part of the brain that generates ideas (higher mental functions, general movement, perception and behavioral responses). The neocortex 240 in humans is organized in six layers, which are parallel to the surface of the cortex. The neurons in the neocortex are organized in cylindrical columns (cortical columns), which are perpendicular to the cortical surface. Axons 140 that traverse vertically in the neocortex 240 typically form connections to neurons within a column, but among the neurons in different layers. Axons 140 that traverse horizontally in the neocortex 240 allow communication between neurons in different columns.

There are two types of memory in the brain: declarative memory and non-declarative memory. Declarative memory is explicit memory and typically depends on the hippocampus 230 and other areas of the brain. Declarative memory includes episodic memory (memory of events from one's life) and semantic memory (general knowledge of the world). The hippocampus 230 retains context-dependent memories until they are consolidated in neocortical structures, but there is evidence that these memories are stored differently in the two structures. Non-declarative memory, on the other hand, is implicit, procedural memory and depends mostly on the basal ganglia and parts of the cerebral cortex (including the neocortex 240). Non-declarative memory is needed to learn skills, such as swimming. For the most part, however, it is still unclear precisely how learning and memory work in the human brain. It is clear that in order for the brain to learn, the structure of the brain must be somewhat plastic; that is, the structure must be able to adapt. Synaptic plasticity dependent on the activity of the synapses is widely thought to be the mechanism through which learning and memory take place. The Hebb rule comprises the idea that if the action potential from one neuron causes another neuron to fire, then the synapse along which the action potential travels should be strengthened (or when a synapse is not used, a decrease in strength). These decreases take place when a particular synapse repeatedly fails to be involved in the firing of a neuron and are supported by experiment.

The effects of these increases and decreases of strength in the synapses can be both short-term and long-term. If the effects last a significant period of time, they are called long-term potentiation (LTP) and long-term depression (LTD). Synaptic plasticity is seen as a process that occurs gradually over time, and the rate of the change can be specified by one or more time constant(s).

Now, the development of artificial neural networks will be discussed, for example, in the context of efforts to simulate the wonders of the human brain. Artificial neural networks can be thought of as directed weighted graphs, where the neurons are the nodes and the synapses are the directed edges. Known neural network architectures are typically made up of input neurons, output neurons and so-called “hidden” neurons. The hidden neurons are those that are neither input neurons nor output neurons in such a network. The structural types include feed-forward neural networks, recurrent neural networks and modular neural networks.

Referring to prior art FIG. 3, there is shown a fully-connected feed-forward neural network comprising input neurons 310-1, 310-2, 310-3, . . . , 310-N to the left and output neurons 330-1, 330-2, 330-3, . . . , 330-P to the right with hidden neurons 320-1, 320-2, 320-3, . . . , 320-M between input and output neurons. It is not shown but one hidden neuron may connect to another hidden neuron. In feed forward neural networks, there is a layer of input neurons, zero or more layers of hidden neurons, and an output layer. Input layers only contain outgoing edges, and the edges of one layer are only connected to the next layer (whether it be a hidden layer or the output layer). Networks may either be fully connected as seen in FIG. 3, in the sense that every neuron in a layer has a directed edge to every neuron in the next layer, or they may only be partially connected, where some of these edges are missing.

Referring now to prior art FIG. 4, there is shown an example of a known recurrent neural network. Recurrent neural networks contain at least one loop, cycle, or feedback path. FIG. 4 shows the input neurons 410-1 to 410-N, output neurons 430 and hidden neurons 420-1, 420-2, . . . , 420-M with the same shading as in FIG. 3. Delay elements 440 are indicated with boxes labeled D. A loop in a directed graph is when there is an edge from a node to itself. Cycles in a directed graph occur when there is a path from a node to itself that contains other nodes. Feedback loops and paths typically involve delay elements D 440. Feedback allows for storage to take place in the neurons; it gives the network a sense of memory from one instance to the next. Recurrent neural networks can be divided further into discrete-time and continuous-time neural networks. Charge is applied periodically or after randomly spaced intervals at inputs at moments in time and propagates through the network, producing no output no earlier than when the charge is applied. Continuous-time neural networks model behaviors such as spikes in the network at infinitesimally small time steps. These spikes are typically modeled using a differential equation rather than as discrete events and may not have a stable solution, especially for networks that contain loops.

A neural network is modular if the computation performed by the network can be decomposed into two or more subsystems that operate on distinct inputs without communication. The outputs of these modules are then combined to form the outputs of the network. A known modular neural network may be one of a recurrent neural network or a feed-forward neural network or other artificial neural network.

Neurons in neural networks are the information processing units of the network. Neurons usually accumulate, combine, or sum signals they receive from their connections, and an activation function is applied to the result. A neuron in the network is said to fire if the output value is non-zero. Several different activation functions are commonly used. There may be a threshold function when the charge reaches a threshold value, a piecewise-linear function sometimes called saturation of a neuron and a sigmoid function related to the slope of increase of charge.

Training in a neural network has canonically meant changing the weights of the connections and/or the threshold values. Relatively recently, training has also referred to changes in the architecture of the network. Neural networks with training algorithms that cannot change the architecture of networks may be considered fixed-structure. Similarly, networks with training algorithms that can change the architecture may be considered variable-structure.

There are two main methods of training: gradient-based methods and evolutionary methods. Back-propagation is the most widely used algorithm for training neural networks in a supervised way. The algorithm is supervised because it requires a set of inputs and their corresponding outputs, called a training set. Back-propagation has two distinct phases: a forward pass and a backward pass. In the forward pass, input signals are propagated through the network, to produce an output. This output is compared with the expected output, producing an error. The error signals are then propagated backwards through the network, where the weights of the networks are adjusted in order to minimize the mean-squared error. Back propagation is a gradient-based optimization technique. It makes use of the gradient of an error function, evaluated using a training data set, with respect to the weights in the network. That is, back propagation uses the gradient of an error to determine how the weights in the network should be changed to reduce the error.

One of the known limitations of back propagation and other supervised learning algorithms is that they typically do not scale well. Gradient-based optimization algorithms have several known limitations as well. Because the weights are changed so that the error follows the steepest direction (in the space of weights) of descent, the results of the optimization algorithm depend largely on the initial starting point. If the initial starting point is located near local optima and far away from the global optimum, the back-propagation algorithm will likely converge to one of the local optima. This is a drawback for the back propagation algorithm because complex systems often have many local optima with significantly different (poorer) performance than a global optimum.

Another known type of training is Hebbian learning. Hebbian learning is analogous to long-term potentiation (LTP) and long-term depression (LTD) that occurs in the brain. In LTP, if the firing of one neuron occurs before the firing of a receiving neuron, then the synapse between these two is strengthened. That is, in LTP, the possibility of a causal relationship between the two neurons (i.e. that the firing of one directly leads to the firing of another), influences how synaptic changes are made. In LTD, the strength of the synapse is decreased when the firing of one neuron does not lead to the firing of its connected neurons, or when the firing of one neuron occurs while the receiving neuron is in a refractory state or has recently fired. In LTD, the possibility of a non-causal relationship between the two neurons influences how synaptic changes are made. For example, if a receiving neuron fired immediately prior to the firing of a transmitting neuron, it may be appropriate to decrease the strength of the synapse.

There are four characteristics of Hebbian synapses. Modifications to a Hebbian synapse depend heavily on time in that increases are made if neurons are activated at the same time, and decreases are made if two neurons are activated at different times. All information required to determine if a change to a Hebbian synapse should be made is local information. That is, the only information required to know if a synapse should change is the activities of the neurons that are connected by that synapse. Changes in the weight of a Hebbian synapse are determined by the firing patterns of the two neurons connected by the weight. Lastly, an increase in the strength of the synapse is caused by the conjunction of presynaptic and postsynaptic activity. Hebbian learning has been observed in biological neural networks. However, applying learning in biological systems to development of learning methods in artificial neural networks is significantly more complicated than these four characteristics imply.

So-called evolutionary algorithms are presently surpassing known, more conventional artificial network architectures. The evolution of the structure of the brain and evolution within the brain can be categorized in four forms. First, at the highest level, there is evolution via speciation, and the brain structure in particular, which has occurred over millions of years. This long-term evolution has affected every aspect of the brain, but most notably, it is the level of evolution where the gross structure of the brain has developed. Following typical evolutionary theory, the complex structures from the human brain evolved from simpler structures that underwent three evolutionary mechanisms: mutation, the introduction of new structures or pieces of structures; recombination, the combination or re-use of existing structures in novel ways; and natural selection, the dying off of unsuccessful structures.

The general structure of the brain does not differ greatly from person to person; there are certain parts of the brain that are present in nearly every individual, though as the evolution of species has occurred these structures have become more complex. These are the types of structures that are, of concern at the level of long-term evolution.

A shorter term evolution of the brain, what will be referred to in this work as moderate-term evolution, has been recently discovered. This evolution, referred to as epigenesis, also affects the structure of the brain, but at a finer level. Epigenesis is caused by modifications to the structure of proteins that regulate the transcription of genes; these modifications are often caused by the environment, but unlike other environmental effects, these modifications can be inherited by future generations through methylation of DNA. The modifications can lead to changes in the structure of the brain and thus far, have been seen to primarily affect the social and affective aspects of the brain.

The evolution (or perhaps more aptly, development and adaptation) that occurs within a single human's brain over the course of a lifetime, from conception through adulthood, will be referred to in this work as short-term evolution. The morphology of the brain is shaped partly through genetics, influenced by both long-term and moderate-term evolution, but also through experience (or by environmental effects). Neurons proliferate and die over the course of an individual's development. One of the factors that affects the formation and survival of neurons in this stage is the way connections are formed, that is, the types of neurons that a particular neuron's axon connects during development. The connections of a neuron affect the way that neuron behaves and operates in the future, and these connections are initially determined during this short-term evolutionary stage. An example of this type of evolution is found in London taxi drivers who have been found to develop significant brain areas for storing road maps of London.

There is a certain amount of plasticity during development that allows an individual to adapt the different parts of the brain (determined by long-term evolution) to his or her particular role. There are certain portions of the brain, such as the neocortex, in which the local structure (i.e. connection strengths) appears to mostly depend on the environment, rather than genetics.

Another major structural aspect of the brain that is evolved or developed over the course of single person's lifetime is myelination. Myelination affects the efficiency and rapidity of transmissions of signals in the brain. Myelination in humans continues well into the second decade of life.

Finally, very short-term evolution (development or learning, in this case) occurs on a day-to-day basis in the brain. This evolution affects synapses; this type of evolution is what is typically referred to as plasticity in the brain. There are four known major types of synaptic plasticity: long-term potentiation, long-term depression, sensitization, and axonal sprouting and formation of new synapses. Long-term potentiation and long-term depression were discussed above within the context of Hebb's rule. Long-term potentiation (LTP) is a permanent or semi-permanent change in the way a neuron fires and is caused by repeated activation with stimulation; it is associated with memory in the brain. Long-term depression (LID) refers to any form of depression in synaptic transmission, such as the lowering of signal transmission efficacy. Long-term potentiation (LTP) occurs only when a synapse is active, but long term depression can occur whether a synapse is active or inactive.

Sensitization refers to enhancement of a response as a result of applying a novel stimulus. Finally, axons can sprout, both during initial formation and after transection, in the brain. Axon sprouting occurs most commonly during neonatal development, but it also can occur in adulthood.

Evolutionary algorithms are optimization algorithms that are often used in large, complex state spaces. Biological evolution is a method for searching a huge number of possibilities for solutions, where solutions are the organisms themselves. The biological inspiration of evolutionary algorithms is described in Flake's “The Computational Beauty of Nature” as follows:

Adaptation=Variation+Selection+Heredity.

In evolutionary algorithms, a population of potential solutions is maintained. The members of the population are usually distinct and maintain variety. Evolutionary algorithms are inherently random, and the random influences contribute to the variety in the population. Selection is perhaps the most important component of the formula given above. Selection refers to the concept of “survival of the fittest.” For evolutionary algorithms, some concept of fitness must exist, where fitness is typically a function or algorithm mapping members of the population to numerical values. It is worth noting that the fitness function can be based on simulated values, so it may generate different value each time it is applied to a member of the population. The fitness of a member of a population should represent the relative ability of that member of the population to perform a particular task. The fittest members of the population are those that are most likely selected to reproduce and express traits that are kept over multiple generations. Members of the population that are the least fit are those that are more likely to be allowed to die off. Heredity is emulated in evolutionary algorithms by producing “offspring” from existing members of a population. The offspring can be produced in a variety of algorithm-specific ways. The sequence of typical operations for producing offspring are reproduction, crossover and mutation.

For reproduction, one or more relatively fit members of the population may be selected to reproduce. Members of the population that have a higher fitness level may be more likely to have offspring in the next generation of the population. The selection of these members of the population can be done in a variety of ways. One of the ways this is done is using Roulette selection. In Roulette selection, a member of the population is randomly selected, where the probability that a given member of the population is selected is based on that population member's fitness. That is, if a member has a high fitness, it is more likely to be selected. Another selection algorithm is tournament selection. In tournament selection, a fixed percentage of the population is randomly selected. From that smaller group, the member with the highest fitness is selected. The percentage selected from the original population is a parameter of this method. For example, if you select 100 percent of the population to be this parameter, then the fittest member of the population would always be selected. However, if you had a population size of 100 and selected one percent of the population, then the selection would be entirely random (i.e. not based on fitness at all).

In crossover, attributes of two or more members of the population are combined to form a new member of the population. Finally, mutation can occur, in which some attribute of the new member is randomly changed in some way. Different types of mutations can be employed, depending upon the complexity of the representation of each member of the population. Both crossover and mutation have associated rates in an evolutionary algorithm. The crossover rate is the percentage of time in which selected members of the parent population are crossed over or combined to produce members of the child population, whereas the mutation rate is the rate at which members of the parent population are mutated to produce members of the child population. Assuming neither of these rates is 1, there may be some propagation of identical members of the parent population to the child population.

Neuroevolution algorithms use evolutionary algorithms to train neural networks. The first neuroevolution algorithms that were developed only evolved the strength of the connections between the neurons; they did not affect the structure by adding or deleting connections or neurons. They only dealt with one form of evolution described above: very short term evolution.

The training of the connection weights in neural networks is typically formulated as an optimization problem. In particular, some error is minimized, or equivalently, a measure of performance or a goal is maximized. These approaches are equivalent because if f(x) is an error function, then 1/1(x) and −f(x) are suitable candidates for goal functions, and vice versa. The error used can be the mean squared error between the actual output and the expected output in supervised learning or the temporal difference error as used in reinforcement learning. Another example goal function is the length of time of successful operation. The weights of the networks are then trained using algorithms such as back propagation or conjugate gradient. These algorithms rely on gradient-based optimization algorithms using steepest or gradient related descent directions. There are many drawbacks to using these gradient-based optimization algorithms. In particular, gradient-based algorithms rely on the differentiability of error or goal functions, and they are likely to converge to local optima.

Evolutionary algorithms had been applied in the field of optimization to similarly complex problems, as they are less likely to become trapped in non-optimal solutions. It was a natural extension to apply evolutionary algorithms to weight training in neural networks, as this problem can be formulated as an optimization problem through which an error is minimized. Xin Yao reviews (to date) works using evolutionary algorithms (EA) to evolve/train artificial neural networks (ANNs), including using EAs to find weights, structure, learning rules, and input features in his “Evolving Artificial Neural Networks,” Proceedings of the IEEE, Vol. 97, No. 9, pp. 1423-1447, September 1999. Yao cites results that indicate the combination of an EA and an ANN result in better systems than EAs or ANNs in isolation. Yao presents a thorough overview of algorithms that use evolutionary algorithms to train the weights of neural networks in “Evolving Artificial Neural Network Ensembles,” IEEE Computational Intelligence Magazine, pp. 31-42, 2008. Yao notes four advantages of evolutionary algorithms to gradient-based algorithms. First, evolutionary algorithms do not depend on gradient information, which may be unavailable or difficult to calculate. Evolutionary algorithms can be applied to any neural network architecture, whereas gradient-based algorithms have to be adapted for different architectures. Evolutionary algorithms are much less sensitive to initial conditions. Evolutionary algorithms always search for global optima, rather than local optima. It is also important to note that evolutionary algorithms typically rely on a fitness function, rather than an error. This fitness function can often be easily translated to reinforcement learning problems, where the fitness function is the reward received. As noted previously, however, goal, or fitness, functions can be used to determine error functions, and vice versa. The most straightforward way to do this is to reverse the sign.

Many known evolutionary algorithms deal with only one form of evolution: very short term evolution. For this type of evolution, the structure of the network is fixed. The structure of the network includes the general architecture (i.e. feed-forward, recurrent, etc.), the number and layout of neurons (i.e. how many neurons should be included in a particular layer), and the number and nature of the connections (i.e. how the neurons should be connected). For these types of algorithms the structure of the neural network is mostly determined via experimentation. That is, a certain structure is tested, and if that structure does not work, more neurons or connections are added manually, increasing the complexity, until the network is able to handle the problem. This requires significant hand-tuning by the experimenter/researcher. Knowledge about the problem can be applied and intuition developed to decide what sort of structure is required by certain problems. For each problem, a new structure needs to be determined and the selection of this structure relies entirely upon the knowledge of the structure designer. Networks with and without bias parameters and networks with different numbers of hidden neurons perform very differently. Because the structure has such a large effect on the efficacy of the network, an algorithm that learns what structure is needed to solve a particular problem is much more attractive than an algorithm that relies on prior knowledge or hand-tuning to design a structure. Constructive and destructive algorithms are algorithms that attempt to deal with this drawback. Both constructive and destructive algorithms attempt to learn a network structure, rather than relying on the trial and error approach. Constructive algorithms start with very small networks and increase their size by adding neurons and connections as needed for a particular problem. Destructive algorithms such as pruning begin with overly complex networks. Connections and neurons are then deleted to yield a minimal structure. These constructive and destructive algorithms would seem to solve the problem of finding a neural network architecture to use. However, there is a fundamental issue with these algorithms. Constructive and destructive algorithms follow strict sets of rules; for example, a constructive algorithm may only be able to add a single neuron at a time to a hidden layer. These algorithms therefore only explore a strict subset of possible architectures.

There are several drawbacks to using conventional evolutionary algorithms. Although the final overall solution may be more optimal than the solution reached by a gradient-based algorithm, evolutionary algorithms typically take longer to find a solution. Applying evolutionary algorithms to neural networks in particular comes with a variety of issues. Important factors include how to represent the networks in the population, how to measure performance and how to create offspring in a population. Evolutionary algorithms usually work with strings of real or binary numbers. There has to be a performance metric to gauge how “fit” a member of the population is. Creating offspring is usually done through mutation, crossover (recombination) or both.

Representations of a network need to maintain a link to the functionality of the network; otherwise, operations such as crossover will have no meaning. Performance is a key metric and is a problem-specific issue. For example, supervised learning problems have an associated error, which would need to be converted into an appropriate fitness function and associated value, while reinforcement learning problems have associated rewards, which would also need to be converted to an appropriate fitness function and have an associated fitness value. The mechanisms of offspring creation are usually closely related to the representation of the networks in populations.

If a network is not performing well enough using just back-propagation (i.e. the error between the expected and produced value has not lowered significantly), simulated annealing can be used. Finally, if it is still not performing well, the architecture can be mutated. Yao referenced above (and Liu) used this approach to attempt to reduce the computational cost of the evolutionary algorithm. They successfully apply their algorithm to several parity tasks. This approach is similar to the proposed hierarchical evolutionary strategy discussed above, in that different types of evolution (very short term, short term, and moderate term) are tried. In particular, the combination of a genetic algorithm at a higher level and another algorithm, such as simulated annealing, numerical optimization methods such as non-linear programming, gradient, generalized gradient, and/or Newton's method, at a lower level can be used.

Montana and Davis in “Training Feedforward Neural Networks Using Genetic Algorithms,” Machine Learning, pp. 762-767, 1989 use genetic algorithms to evolve the weights in a feed-forward neural network. They represent their networks as a list of real numbers and use mutation, crossover and gradient operators to create offspring. They successfully apply their algorithm to classification of sonar data, compare to back-propagation and incorporate domain-specific knowledge. However, their application to some real-world problems is hampered by the lack of a training algorithm for finding an optimal set of weights in a relatively short time.

D. B. Fogel et al. in “Evolving Neural Networks,” Biological Cybernetics 63, pp. 487-493, 1990, use genetic algorithms (GA) to evolve the weights in a feed-forward neural network, but also note that GAs will also work for other models, such as recurrent neural networks. They represent their networks as a list of real numbers and use only mutation to create offspring. They apply their algorithm to exclusive-or and a blending problem and compare to back-propagation, with favorable results.

Xin Yao and Yong Liu introduce an evolutionary system called EpNet for evolving the architecture and weights of feed-forward artificial neural networks in “A New Evolutionary System for Evolving Artificial Neural Networks,” IEEE Transactions on Neural Networks, 8, pp. 694-713, 1997. Yao and Liu attempt to maintain a behavioral link between parent and child by using node splitting rather than adding a fully connected node to a layer. EPNet also encourages simplicity in the network by always testing to see if a deletion will improve the network before testing an addition. They applied EPNet successfully to parity problems, medical diagnosis problems and time series prediction problems. They found that their networks generalized better than other networks developed or trained using other methods. This is one of the reasons a neuroevolution approach was selected for an embodiment of the present invention.

Yao and Liu introduce five mutation operations that, again, are chosen in succession to maintain simpler networks if possible. The five mutation operators they introduce (given in the order they are tried) are: hybrid training (train using a modified back propagation algorithm), neuron deletion, connection deletion, connection addition, and neuron addition.

Dario Floreano et al. in “Neuroevolution: from architectures to learning,” Evol. Intel. 1, pp. 47-62, 2008, apply artificial neural networks to many real-world problems ranging from pattern classification to robot control. A generic architecture shown in their FIG. 1 is similar to that depicted in FIG. 3 wherein the external environment is connected to input neurons and output units impact the external environment. They describe a continuous-time recurrent neural network or CTRNN. These CTRNN's represent a first approximation of the time-dependent processes that occur at the membrane of biological neurons.

Randall D. Beer and J. C. Gallagher in “Evolving Dynamical Neural Networks for Adaptive Behavior,” Adaptive Behavior, pp. 91-122, 1992, use evolutionary algorithms (EA) to train continuous-time recurrent neural networks (CTRNNs). They use dynamical parameter encoding to encode chromosome representing the network and use both crossover and mutation operators. They apply their CTRNNs to a food-finding task and a locomotion task (with six-legged agents).

A. P. Wieland in “Evolving Neural Network Controllers for Unstable Systems,” Neural Networks, 2, pp. 667-673, July, 1991, uses a recurrent neural network model that learns weights and connections between neurons. A binary representation is used to represent the network, and mutation, crossover, and inversion operations are used to produce offspring. This method is applied to variations on the pole balancing problem (single pole, double pole, jointed pole, and two-legged walker).

S. Dominic et al. in “Genetic Reinforcement Learning for Neural Networks,” Neural Networks, 2, pp. 71-76, 1991, compare genetic algorithms to reinforcement learning techniques. They use a feed-forward neural network, and real-valued strings are used to represent the networks. They apply their network and algorithm to the pole balancing problem and compare their results to a reinforcement learning method (Adaptive Critic Heuristic).

K. Stanley and R. Miikkulainen in “Evolving neural networks through augmenting topologies,” Evolutionary Computation, 10(2):99-127, 2002, introduce Neuroevolution of Augmenting Topologies (NEAT), which has several innovations, including speciation to protect structural innovation, global innovation numbers to do historical tracking of network structure and help avoid the competing conventions problem, and makes use of incremental growth to avoid unneeded complexity in the networks. NEAT is applied to exclusive-or and to two pole balancing problems (with and without velocities). They demonstrate that NEAT performs better than other neuroevolution methods on these tasks and demonstrate that the improvement in performance is due to those innovations.

K. Stanley, et al. in “Evolving adaptive neural networks with and without adaptive synapses,” Evolutionary Computation, 2003, CEC '03, The 2003 Congress on, 4: 2557-2564, 2003, augment NEAT by including adaption of learning rules (such as local Hebbian learning rules) for each connection as part of the evolution. This allows for adaptation of networks to changes in the environment and is related to the ability to the network to do real-time learning. They apply this version of NEAT to a dangerous foraging example.

Jeff Hawkins et al. in “Sequence memory for prediction, inference and behavior,” Phil. Trans. Royal Soc. B, pp. 1203-1209, 2009, describe a mechanism for storing sequences of patterns necessary for making predictions, recognizing time-based patterns and generating behavior. They suggest that the ability to store and recall time-based sequences is probably a key attribute, of many, if not all, cortical areas. They propose that the neocortex may be modeled as a hierarchy of memory regions, each of which learns and recalls sequences.

Artificial neural networks are known implemented in “hardware” as may be distinguished from more “software” embodiments. For example, Glackin et al. in “A Novel Approach for the Implementation of Large Scale Spiking Neural Networks on FPGA Hardware,” IWANN 2005, LNCS 3512, pp. 552-563, 2005, implemented a large scale spiking neural network on field programmable gate array (FPGA) hardware. A neuron, synapse, and spike timing dependent plasticity (STDP) blocks are implemented in FPGA logic, and neural network data are held in SRAM that is external to the FPGA device. Synapse weights are determined by spike timing dependent plasticity (STDP).

In 2007, Cassidy et al. in “FPGA Based Silicon Spiking Neural Array,” Biomedical Circuits and Systems Conference (BIOCAS 2007), pp. 75-78, IEEE, 2007, present a FPGA based array of Leaky-Integrate and Fire (LIF) artificial neurons. Their neurons and synapses were fixed, and each synapse supported a “single” event and a delay function associated with the event. The synapses were able to implement STDP.

In U.S. Pat. No. 7,533,071, entitled “Neural Modeling and Brain-based Devices Using Special Purpose Processor” and issued to Snook on May 12, 2009, discloses a further FPGA hardware embodiment. Snook uses a special purpose processor and FPGAs to model a large number of neural elements. Each core of the FPGA could do presynaptic, postsynaptic, and plasticity calculations in parallel. It could also implement multiple neural elements of the neural model. The network was used to control a robot.

Sharp et al. in “Power-efficient simulation of detailed cortical microcircuits on SpiNNaker,” Journal of Neuroscience Methods, 201, pp. 110-118, 2012 simulate an anatomically-inspired cortical microcircuit of ten thousand neurons and four million synapses using four SpiNNaker chips and less than two watts. The neuron model was very basic but consumed little power. Each chip consisted of 18 homogeneous processors.

It is known to utilize or implement central pattern generators with artificial neural networks. M. Anthony Lewis et al. in “Control of a robot leg with an adaptive a(nalog)VLSI CPG chip,” Neurocomputing, 38-40, 2001, pp. 1409-1421 constructed an adaptive central pattern generator (CPG) in an analog VLSI chip, and uses the chip to control a running robot leg. A pacemaker neuron is used to control the firing of two motor neurons. Sensors are excited and inhibited the pacemaker, allowing the robot to adapt to changing conditions.

Thereafter, M. Anthony Lewis et al. in “CPG Design Using Inhibitory Networks,” Proc. of the 2005 IEEE International Conference on Robotics and Automation, (ICRA 2005), pp. 3682-3687, 2005, implemented CPGs that are designed and optimized manually. A four-neuron, mutual inhibitory network forms the basic coordinating pattern for locomotion. This network then inhibited an eight-neuron network used to drive patterned movement.

It is also known to utilize analog circuitry for the construction of artificial neural networks. Simon Friedmann et al. in “Reward-based learning under hardware constraints—using a RISC processor embedded in a neuromorphic substrate,” Frontiers in Neuroscience, 7, p. 160, 2013 proposed and analyzed in simulations a flexible method of implementing spike time dependent plasticity (STDP) in a single layer network on a wafer-scale, accelerated neuromorphic hardware system. Flexibility was achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. It was possible to flexibly switch between synaptic learning rules or use different ones in parallel for different synapses.

U.S. Pat. No. 8,311,965 entitled “Area Efficient Neuromorphic Circuits Using Field Effect Transistors and Variable Resistance Material” issued to Breitwisch et al., Nov. 13, 2012, provides details for analog neuromorphic circuits using field effect transistors. Manually programmable resistances are implemented using phase change material.

U.S. Published Patent App. No. 2012/0109863 entitled “Canonical Spiking Neuron Network for Spatiotemporal Associative Memory,” on May 3, 2012, to Esser et al. presents a layered neural net of electronic neurons configured to detect the presence of a spatiotemporal pattern in a real-time data stream, and extract the spatiotemporal pattern. The plurality of electronic neurons stored the spatiotemporal pattern using learning rules (STDP). Upon being presented with a version of the spatiotemporal pattern, they retrieved the stored spatiotemporal pattern.

U.S. Pat. No. 8,600,919 entitled “Circuits and Methods Representative of Spike Timing Dependent Plasticity of Neurons,” to Poon et al., Dec. 3, 2012, describes a circuit and a method that could emulate STDP in a way that closely replicated biochemical processes, that could emulate all of the different types of STDP, and that could provide a relationship between the Bienenstock-Cooper-Munro rule and STDP.

U.S. Published Patent App. 2009/0292661 entitled “Compact Circuits and Adaptation Techniques for Implementing Adaptive Neurons and Synapses with Spike Timing Dependent Plasticity (STDP)” on Nov. 26, 2009, to Hass implements STDP using a simple analog circuit.

U.S. Pat. No. 8,510,239 entitled “Compact Cognitive Synaptic Computing Circuits with Crossbar Arrays Spatially in a Staggered Pattern” issued to Dharmendra S. Modha, Aug. 13, 2013, implements STDP using electronic neurons interconnected in a compact crossbar array network. Neurons could be implemented to include a “leak” function. The invention could be realized in an entirely hardware form, an entirely software form, or a hybrid software/hardware form.

U. S. Published Patent Application No. 2012/0036099 entitled “Methods and Systems for Reward-Modulated Spike-Timing-Dependent Plasticity” on Feb. 9, 2012, to Venkatraman et al. describes an area-efficient implementation of reward-modulated STDP. Three separate memories with entries for each synapse were used. The first two memories stored current and updated synapse weights, and the third was used to determine if the weight needed to be updated.

U.S. Pat. No. 8,433,665 entitled “Methods and Systems for Three-Memristor Synapse with STDP and Dopamine Signaling” issued to Tang et al., Apr. 30, 2013, proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling. One memristor could be utilized for long-term potentiation (LTP), another for long-term depression (LTD), and the third as a synaptic connection between a pair of neurons with a variable strength.

U.S. Pat. No. 8,515,885 entitled “Neuromorphic and Synaptronic Spiking Neural Network with Synaptic Weights Learned Using Simulation” issued to Modha, Aug. 20, 2013, used computer simulation to determine synaptic weights which were loaded onto chips. Simulation was abstract and could be done using spike-timing dependent plasticity (STDP) or reinforcement learning. External learning allowed for small, efficient neuromorphic hardware systems.

U. S. Published Patent App. No. 2013/0073497 entitled “Neuromorphic Event-Driven Neural Computer Architecture in a Scalable Neural Network” on Mar. 21, 2013, to Filipp Akopyan et al. presents a spike event driven network where axons are connected to neurons by a synapse array. It uses a scheduler to deliver spike events to axons. Each neuron maintains a STDP variable that encodes the time of the most recent fire. It is used to implement LTP/LTD.

B. V. Benjamin et al. in “Neurogrid: A mixed-analog-digital multichip system for large-scale neural simulations.” Proceedings of the IEEE, 102, pp. 699-716, 2014 created Neurogrid, an entirely clockless system with sixteen mixed-analog-digital chips that simulated a million neurons with billions of synaptic connections in real time using sixteen Neurocores integrated on a board that consumed three watts. STDP was possible, but at a high cost to area, time, and energy efficiency.

Giacomo Indiveri et al. in “Neuromorphic silicon neuron circuits.” Frontiers in Neuroscience, 5, 2011 described “the most common building blocks and techniques used to implement” silicon neuron circuits and “compare[d] the different design methodologies used for each silicon neuron design described, and demonstrate[d] their features with experimental results, measured from a wide range of fabricated VLSI chips.”

Cassidy et al. in “Cognitive Computing Building Block: A Versatile and Efficient Digital Neuron Model for Neurosynaptic Cores,” IBM Research, 2013, presented TrueNorth, a scalable neurosynaptic computer architecture, which used leaky integrate-and-fire neurons. The input, the state, and the output were implemented with configurable and reproducible stochasticity. The invention has four leak modes that bias the internal state dynamics, deterministic and stochastic thresholds, and six reset modes for rich finite-state behavior.

Preiss et al. in “Compass: A scalable simulator for an architecture for cognitive computing,” Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis, p. 54. IEEE Computer Society Press, 2012 presented Compass, a multi-threaded, parallel functional simulator of the TrueNorth architecture. It successfully simulates 10⁹ neurons and 10¹² synapses at 388 times slower than real time. It is event driven, not clock driven.

WO Patent App. 2004/027704 published Apr. 1, 2004, entitled “Spiking Neural Network Device,” by Dario claims a device that stores a genotypic representation of a spiking neural network. Evolutionary algorithms are used to tailor networks to be used in control systems.

Gomez et. al. in “Efficient Non-linear Control Through Neuroevolution,” Machine Learning: ECML 2006, LNCS 4212, pp. 654-662, 2006, introduce CoSyNE, a neuroevolution method that evolves recurrent neural networks at the weight-level. Networks are represented as a vector of real-valued weights, children networks are created using crossover and mutation, and networks are co-evolved by permuting subpopulations to allow for an increase in diversity. CoSyNE is compared with a large number of reinforcement learning and neuroevolution methods on the one and two pole balancing task. In their follow-up “Accelerated Neural Evolution through Cooperatively Coevolved Synapses,” J. Mach. Learn. Res., 9: pp. 937-965, 2008, Gomez et al. discuss CoSyNE in detail, as well as compare it with several reinforcement learning and neuroevolution methods. This work presents results for sixteen methods in total (including CoSyNE) on one pole and two pole balancing tasks, with and without velocities provided as input. The results demonstrated that neuroevolution methods perform better than reinforcement learning methods, and that CoSyNE performed the best of the neuroevolution methods tested.

Notwithstanding the advances in evolutionary artificial network architectures and algorithms, there remains a need for an improved neuroscience-inspired network architecture which overcomes the problems exhibited by known architectures.

SUMMARY OF THE PREFERRED EMBODIMENTS

In accordance with an embodiment of a method and apparatus for constructing a neuroscience-inspired artificial neural network in the form of a dynamic adaptive neural network array (DANNA) of basic neuron and synapse elements that may be constructed of field programmable gate arrays that overcomes the deficiencies of the prior art, the embodiment exhibits five characteristics which differentiate over the prior art. Firstly, it is desirable that a neural network structure evolve over time. Evolution over time means that the learning algorithms of the prior art may not evolve in accordance with data (events) received at input neurons compared with the evolution achieved in accordance with the present invention and the present learning algorithms disclosed herein. Secondly, it is desirable that neural networks may be embedded into a geometric space. This characteristic suggests that the present invention seeks confinement, for example, to a geometric space in a similar manner that it is believed that the human brain and its sensory inputs and outputs are confined to a geometric space. Thirdly, it is desirable that neural networks compose dynamic elements and operate on a continuous time scale. In some embodiments, a discrete time scale may be preferred, for example, for digital or discrete time unit measurement. By dynamic elements is intended the opposite of static elements such as dynamic neurons and dynamic synapses. Also, the concept of continuous time scale means an intention to differentiate from a discrete time scale or one capable of one input at a time, such as one per clock period when the clock period may be increased or decreased in length. Clearly, it is desirable if an artificial neural network is able two receive two inputs at the same time, that is, all inputs are continuously occurring and the network is continuously learning and making decisions with the expectation that the artificial neural network will adapt to its environment. Fourthly, it is desirable if useful substructures in neural network structures can be recognized and reused. That is, for example, the present invention is capable of identifying in a visualization those structures that are acting in response to a given input or continuous series of inputs. Then, theoretically, these same structures that have been identified may be reused to respond to a similar set of inputs. Fifthly, it is desirable if special-purpose emotion-related substructures and neurotransmitters can be incorporated into artificial neural networks. As suggested above, emotions such as fear or anger have been artificially simulated in the prior art individually but not collectively as to the collection of many emotion-related substructures.

An artificial neural network according to an embodiment of the present invention initially comprising a two-dimensional or three-dimensional structure in space comprises input neurons, hidden neurons and output neurons connected by synapses. Synapses in embodiments of the invention encompass the concepts of axons and dendrites. In other words, “synapse” is used to describe connections between neurons. Input neurons receive stimulus (data) from the environment. Output neurons cause a result in the environment. Hidden neurons are connected by synapses between input neurons and output neurons. An exemplary DANNA may comprise, for example, two thousand five hundred elements, specifically, neurons and synapses constructed from field programmable gate arrays in a two dimensional or three dimensional spatial structure operating in real time (or intentional slowed time for neural pathway analysis). Desirably, at least one affective system may be coupled to the artificial neural network for regulating at least one parameter associated with a neuron or a synapse and, preferably, may adjust that same parameter for each impacted like element in the network, neuron or synapse. In particular, a demonstrated affective system changes the thresholds of neurons in the network, which is analogous to a neurotransmitter in the brain making neurons more or less likely to fire. Consequently, a neuroscience-inspired artificial neural network architecture (NIDA) may comprise, for example, three such networks, coupled in simulated three dimensional space. For example, a NIDA may comprise a neuroscience-inspired dynamic architecture comprising of a computational network and first and second affective networks which may provide a simulation of LTP and LTD. This embodiment may be simulated on a well-known von Newman computer processing system so as to comprise a special purpose processing system for solving problems in control (a pole balancing problem by way of example), anomaly detection (data arrival rates at a node in a data network by way of example) and classification (recognition of hand-written numbers by way of example).

Moreover, simple neuron and synapse elements have been constructed in “hardware” to build two dimensional and three dimensional artificial networks for performing the same control, anomaly detection and classification problems. Preferably, one circuit element may comprise either a neuron or a synapse (selectively). That is, a circuit element as described may be a neuron or a synapse but not both at the same time. These simple elements utilize the same parameters as those of the simulated networks. The simple circuit elements may be constructed into dynamic adaptive neural network arrays (DANNA's) having multiple levels of interconnections among neurons and synapses. Both the simulated and hardware embodiments are continuously evolving over time under the influence, for example, of the affective networks and learning.

These and other embodiments and the control, anomaly detection and classification problem solutions will be discussed in some detail in the Detailed Description section and are introduced in the Brief Description of the Drawings section which follows.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of a method and apparatus for predicting object properties will be discussed in the context of the following drawings wherein:

FIG. 1 is a prior art diagram showing selected features of a typical neuron and its components.

FIG. 2 is a prior art diagram of the human brain and some of its components.

FIG. 3 is a prior art representation of a fully-connected feed-forward neural network showing input neurons, so-called hidden neurons and output neurons.

FIG. 4 is a prior art representation of a recurrent neural network with input, hidden and output neurons, the representation having delay elements labeled D.

FIG. 5 is a pictorial representation of crossover with three dimensional representations of Parent 1, Parent 2, Child 1 and Child 2.

FIG. 6 is a flowchart showing a process of crossover, which is related to Parent 1, Parent 2, Child 1 and Child 2 crossover FIG. 5.

FIG. 7A is a flowchart showing a training method using tournament or roulette processes.

FIG. 7B is a flowchart showing the formation of a child population from a parent population introduced as block 724 of FIG. 7A.

FIG. 8 shows coupled, simulated neuroscience-inspired neural networks comprising a computational network and at least one affective network (two affective networks shown).

FIG. 9A shows a diagram of a single array element that may implement all the functions necessary to support its operation as either a neuron or a synapse assuming 8 inputs; FIG. 9B shows a similar diagram of a single array element for either a neuron or synapse assuming 16 inputs; FIG. 9C is a simple diagram of a pass-thru element having 8 inputs from 8 different outputs for the array element of FIG. 9A.

FIG. 10A provides a high-level block diagram of the array of elements and the programmatic and control functional elements.

FIG. 10B shows the high-level block diagram of the array of elements of FIG. 10A with selected elements configured to implement an exemplary artificial neural network, interface and control circuitry, configuration circuitry, an interface to an external process, and a control and optionally optimizing device.

FIG. 10C provides a clock time diagram for the clocks shown in FIG. 9A, FIG. 9B and FIG. 10A.

FIG. 11 shows an exemplary array of elements of a DANNA having exemplary elements 1110 and 1130, each element having at least one input or output signal line exemplified by signal line 1120.

FIG. 12A shows a subset of the exemplary array of elements of FIG. 11.

FIG. 12B shows a representative four by four block of elements comprising neurons N and synapses, the synapses represented by arrows.

FIG. 12C shows four (4) four by four blocks of elements showing an overlapping dark gray loop through certain neuron and synapse elements 1224 that overlaps a second light gray loop 1222 of neurons and synapses.

FIG. 13 shows an array of elements with space added between elements for clarity.

FIG. 14 shows an array of elements with connections illustrated as lines.

FIG. 15 shows an array with a second set of connections, skipping every other element.

FIG. 16 shows four sets of level-2 interconnection networks illustrate by shaded circles representing the elements that participate in each level-2 network.

FIG. 17 shows in addition to a level-2 network a level-3 network of connections between selected elements, indicated by bold circles around those elements.

FIG. 18 shows the network of FIG. 16 having an additional level-5 network of connections between selected elements, indicated by bold circles around those elements.

FIG. 19 shows a DANNA illustrated with level-5 connections among six of the elements, as shown in FIG. 18, without the shading indicating the level-2 interconnection network.

FIG. 20 shows a DANNA of X columns and Y rows of circuit elements having an output register for selectively receiving outputs from read registers of the X columns of circuit elements which may be monitored by an element monitoring process.

These figures will be further described in the detailed description of embodiments of a DANNA which follows.

DETAILED DESCRIPTION

Embodiments of a method and apparatus for constructing a neuroscience-inspired artificial neural network in the form of a dynamic adaptive neural network array (DANNA) will be described with reference to FIGS. 1-20. One embodiment comprises a computational network and may include no affective system or one or more affective systems of different complexity. One embodiment may comprise a neuroscience-inspired dynamic architecture or combination of substructures of each a DANNA and a NIDA or other artificial neural network known in the art.

The design of the artificial neural networks described herein draws inspiration both from biological neural networks and from traditional artificial neural networks from machine learning. It is important to note that a goal is not to directly simulate a biological network, and the simulations described herein are not intended to represent what occurs in the brain. A model of a neuron may be extremely simplified. Even with the relatively simple neural implementation used herein, complex behavior may be generated by trading off complexity of the neuron for complexity in the network.

In one implementation, each neuron is located at a point in a two-dimensional or a three-dimensional space. Referring briefly to FIG. 8, neurons can be input neurons 810, output neurons 890, both types, or neither type, depending on the requirements of the network. For example, an input from a process 810 is input to computational network 820 having two input neurons shown by way of example. Each neuron has an associated threshold and refractory period. In exemplary implementations, both of these values are fixed for the network (i.e., every neuron in the network has the same threshold and refractory period), but an alternate implementation would allow for selected and possibly all neurons to have different threshold and refractory period. Neurons are connected to other neurons via synapses. These synapses are directed, so each neuron has a set of synapses to other neurons and a set of synapses from other neurons. The primary actions of a neuron are changes in charge and in firing. Charge is received by a neuron from its synapses. As is the case in biological neurons, synapses may be inhibitory (negative), in which case the firing of a neuron at one end of a synapse results in a decrease in charge at the neuron a the other end of the synapse, or they may be excitatory (positive), in which case the firing of the neuron at the one end results in a increase of charge at the neuron at the other end. The charge on a neuron is accumulated until that neuron's threshold is reached.

When the threshold is reached, if the neuron is not in its refractory period, the neuron fires, and the neuron's charge is reset to zero (or neutral, as the charge may also be negative). If the neuron is within its refractory period, then, the neuron maintains its charge but does not fire. Thus, a neuron can accumulate charge during its refractory period, but it cannot fire during this period. As soon as a neuron fires, it enters its refractory period. One function of the refractory period is to place an upper limit on firing rate or frequency. This model of a neuron is inspired by the Hodgkin-Huxley model. In the present model discussed, the charge values and threshold values of the neurons may be bounded between −1 and +1.

Neuron thresholds and refractory periods, and synaptic propagation delays all may introduce dynamic behaviors in the present network (especially if these parameters are permitted to vary). Two synapses may be linked together, their delays being additive. Unlike most proposed ANN architectures, but similar to natural neural processes, these dynamic effects are distributed throughout the present network and are directly influenced in the generated ANN's by the evolutionary optimization methods used to construct and adapt the ANN's for specific purposes.

Synapses in the implementation discussed herein are defined by the neurons they connect. Specifically, each synapse goes from one neuron to another neuron. Each synapse has a distance between two neurons and a weight (or strength) of the synaptic connection. The distance between the two neurons affects how long it takes for charge to travel along the connecting synapse and the weight of the synaptic connection determines how much charge arrives at the second neuron after the first neuron fires. Alternatively, a time delay may be used instead of a distance. In this case, the positions of neurons are optional. As is the case in biological neurons, synapses may be inhibitory (negative), in which case the firing of neuron at one end of the synapse results in the decrease of charge at the neuron on the other end, or they may be excitatory (positive), in which case the firing of the neuron at one end results in the increase of charge at the neuron on the other end. One network model discussed herein does not include the concept of myelination (fat growth which decreases delay); if two synapses are each of length d, then, it takes the same amount of time for charge to travel from one end of each synapse to the other. A second network model may simulate myelination using a propagation velocity parameter associated with each synapse, or selected synapses. The weight of the synaptic connection determines how much charge arrives at the second neuron after the first neuron fires.

Two actions associated with synapses are processes similar to long-term potentiation (LTP) and long-term depression (LTD). LTP and LTD occur in biological brains. It is speculated that they play a major role in learning. If charge traveling along a synapse from neuron A to neuron B causing neuron B to fire, then, the weight of that synapse increases. In one implementation discussed herein, LTD occurs at that synapse if charge is received by neuron B during its refractory period. LTP increases the weight of the synaptic connection by a fixed value (specified for the entire network or a class of synapses), and LTD decreases the weight of the synaptic connection by the same fixed value. Synapses have a refractory period associated with LTP and LTD, which prevents changes to the weights from occurring too rapidly.

It is important to note that, for many purposes, LTP and LTD could have been omitted altogether. However, a goal of the present work is to use an affective system to control or to modulate the behavior of a neural network that is learning to perform a certain task. Learning for such networks causes not only the synapse weight values to change, but also the structure of the network to change. To demonstrate that an affective system can, in fact, control a learning network's behavior, some form of learning is included in the network. In a simple pole balancing example discussed herein, learning is more complex because the structure of the network also changes over time. Anomaly detection and classification will be discussed herein after control applications such as solving the pole balancing problem.

The networks used for pole balancing are defined on a grid in three-dimensional space. Maximum x, y, and z (called M_(x), M_(y), M_(z)) magnitudes are defined below by way of example, as well as the granularity δ>0 of the grid. Neurons may be located at coordinates in the grid, (x, y, z), where −M_(x)≦x≦+M_(x), −M_(y)≦x≦+M_(y), and −M_(z)≦z≦+M_(z), and the values of x, y, and z may be integral multiples of the granularity δ. We may alternatively define the maximum and minimum x, y and z in the network to form alternative grid shapes in two dimensional or three dimensional space. The granularity parameter specifies how close two neurons in the grid can be. Other approaches may be used in two or three dimension space (or over time, or another fourth dimension).

Simulations may take place at the network level and are discrete-event simulations. Networks may have associated event queues, in which different event types are specified to occur at some time in the simulation. A unit of simulation time is the amount of time it takes for charge to travel one unit in space. For example, if two neurons are connected and are located one unit apart (i.e. a neuron at (0,0,0) and a neuron at (0,0,1)) then one unit of simulation time is the amount of time required for charge to travel from one of the neurons to the other.

Five example event types are defined: addition of charge to a neuron, firing a neuron, adjustment of thresholds, an input pulse event, and a change in the desired firing rate. The addition of charge to a neuron and the firing of a neuron are internal events, which are caused by other events within the network. Input pulse events are events in which the network interacts with its environment. The adjustment of a threshold or threshold event is an interaction of the network with the simulated affective system (or systems). The change in the desired firing rate event is an interaction between the environment and the simulated affective system. Output events, in which the network gives information to the environment, can be defined for applications, such as the pole balancing application of a control category of applications discussed in the results section.

The adjustment of thresholds event type preferably applies a network-wide change to the threshold of every neuron in the network but may apply the change to only selected increased (or decreased) thresholds. The amount to change the threshold is determined by the affective system. The current firing rate of the network and the desired firing rate of the network are inputs to the affective system. The output of the affective system is the amount to change the thresholds by in the network.

A n affective system 840 (FIG. 8A) (or 880 of FIG. 8A) may be used and receive an input 830 (or 870) and provide an output to computational network 820 as well as provide an input 850 and receive an output 860 from a second affective system 880 which may also receive an input 870 from and provide an output to computational network 820 (which in turn provides an output to a process 890). A n affective system may be determined by the following equations, which could be replaced by a second neural, or discrete-event, network. f_(t) is the firing rate of the network, measured over a certain window, at time t. This is the input provided to the affective system from the network. d_(t) is the desired firing rate at time t. This desired firing rate is provided by the environment and can be changed by a desired firing rate event. The error at time t, e_(t), is calculated:

e _(t) =f _(t) −d _(t).  (1)

There may be no affective system, one affective system or two or more affective systems: for example, a simple affective system 840 with two parameters and a slightly more complex affective system with three parameters. The simple affective system may be used in some simulations and not a complex system or vice versa. Both a simple and a complex affective system may have the parameter w>0, which is the window size of the system and specifies how often the error is recalculated. In the simple affective system, the change in the threshold at time t is calculated:

Δτ_(t) =αe _(t).  (2)

The parameter a is a weighting term, and the change in the threshold at each time step is proportional to the firing rate error. Δτ_(t) is the amount that every threshold (or each selected threshold) in the network is changed at time t. This result is passed back to the network, and the change is applied to all of the neurons in the network (or the selected subset); if all, since all of the neurons have the same initial threshold value of 0.5, all neurons in the network maintain the same threshold value throughout the simulation (except in the pole balancing task). The threshold is bounded to be in the interval [−1, +1], and equation (2) has no effect if it would cause either bound to be violated.

In the more complex affective system, a second parameter, λ, is added. A geometrically averaged error at time t, E_(t) is calculated:

The parameter λ may be a decay rate. It defines how much errors at times 0 through t−1 will affect the change in the threshold at time t. With this second affective system, the change in the threshold at time t is calculated:

Δτ_(t) =αE _(t)  (4)

where, again, α is a weighting term. In both cases, the result Δτ is passed back to the network, and the change is applied to all of the neurons in the network. Note that the first and second systems are equivalent if λ=0. The same boundary logic applies as with equation (2).

A goal is to demonstrate that a simple affective system interacting with an artificial neural network can have a noticeable effect and can stabilize the average firing rate at desired levels. All networks discussed in this example (except for those trained to complete the pole balancing task) have 1000 neurons and 10,000 synapses, where M_(x)=M_(y)=M_(z)=100. This is a relatively large artificial neural network, but compared to the human brain, this is a very small network. It is important to note, however, that we are not attempting to model a biological neural system with our artificial neural networks; our artificial neural networks are merely motivated by biology. The tasks these artificial networks are applied to are specific and well-defined. As such, they can be thought of as analogs to the small portions of the neocortex that implement specific functionalities. Networks with different numbers of neurons and synapses yield similar results, though they are not shown in this work.

The initial neuron placements in the network are random, and the distribution of the synapses is random, but with a higher likelihood of connectivity between spatially close neurons than neurons that are farther apart. In this network structure, there are 200 possible x-coordinate values, 200 possible y coordinate values and 200 possible z coordinate values, resulting in 8×10⁶ possible locations for neurons in this exemplary network. A specific instance or realization of an exemplary network may have neurons at 1000 of these locations, randomly selected according to a uniform distribution, except no two neurons are allowed to occupy the same location.

A typical network may have a single input neuron that receives information from the environment. The control, for example, pole balancing network may have many input neurons. The “environment” in a setup consists of two things: pulses sent to the input neuron at, for example, exponentially-distributed random intervals, with a mean firing rate of 0.1 firings per unit time, and an input to the affective system that sets the current desired firing rate, in this example, for the aggregate of all neurons in the network. This input plays the role of a persistent external excitation used to initiate and promote firing events in the network. This is an extremely simple environment; more complex tasks have richer environments that provide meaningful information to the network and receive signals produced by the network. The affective system may monitor the behavior of the network and applies the threshold changes to the network every w (the window size) units of simulation time. For all of the tests in this example, by way of example, w=10.

All neurons in the network may have a refractory period of one, which means that there is an upper limit on the firing rate of the network; since each neuron can fire at most once in a single simulated time step, the maximum firing rate of the network per time step is 1000. This assumes that the network is fully connected, which is not a requirement placed on the random initialization of the networks. There may be neurons that have no incoming synapses or neurons with no outgoing synapses, which would further limit the maximum firing rate of the network, and the network is not necessarily connected.

In preliminary experiments, the parameters of the affective system are set to be α=0.001 and w=10. The long-term potentiation/long-term depression refractory periods are set to be 10, and the weights are adjusted up (for LTP) and down (for LTD) by 0.001. The parameters used in a pole balancing control task may be slightly different and are described in the Table 1 below.

TABLE 1 Network and Affective System Parameters Parameter Value M_(x) 100 M_(y) 100 M_(z) 100 Network granularity δ 1 A 0.001 Λ 0 LTP/LTD refractory 100 steps of simulated time Amount LTP/LTD adjusted 0.001 Window size w 20

A fitness function is defined for each application (control, anomaly detection and classification), and parents may be selected using tournament selection. Networks are represented and manipulated directly in this implementation. Both crossover and mutation operations are applied with some probability to the parents selected. An example of crossover is shown in FIG. 5 and a corresponding flowchart in FIG. 6. Details about the crossover and mutation operations as they apply to our network structures without affected systems are discussed with reference to FIG. 6.

At 602, there is a choice made of two random neurons to specify a plane (for example, a point and a second vector defining a point orthogonal to the plane. At 604, let parent X be 1, child A be 1 and child B be 2. Process 606 distributes parent X's neurons to children. Step 630 asks are there neurons in parent X that have not been passed down. If Yes, at 632, a neuron is gotten that has not been passed down; otherwise, if No at 620, Parent X is set to =1 at 624. From 638, the signed distance to the plane, d, is calculated at 642. Based on d's calculation at 642, the neuron is sent to one of the two children in 660. If d is greater than or equal to 0 at 644, and so Yes at 610, then, the process passes to child A at 612, and if No to child B at 648 and the path 608 from one of 612 or 648 returns to 630; therefore, both conditions 660 are properly handled.

From 624, if Yes at 622, the parent X=2, Child A=2 and Child B=1 at 618 and by arrow 616, the process returns to process 606 to distribute parent X's neurons to children. On the other hand, if the answer is No at 626, then Child X=1 at 628 and, at 636, process 634 begins with respect to child X. For each neuron in child X, at 640 let p be the corresponding neuron in the parent. At 646, for each synapse from p to another neuron, t, in the parent, at 650, is there a neuron m in Child X at t's location at 650? If Yes at 654, then, connect n and m in Child X at 670. If No at 652, let m be the neuron in Child X closest to t's position and connect n and m in Child X at 670. From 670, 668 leads to 666 which asks is Child X=1 and if not, the crossover is complete. If Child X is 1 and Yes is returned at 662, then Child X is set to 2 at 658 and the process for child X 634 begins again at 636.

Both crossover and mutation operations are altered slightly to compensate for the inclusion of the simple affective systems. In particular, the desired firing rate is included as part of the training. An example of a training algorithm is described by way of example with reference to FIG. 7A.

Referring to FIG. 7A, there is provided a flowchart of an exemplary training algorithm utilizing tournament or roulette processes 712. At 714, the training permits a user to specify a number of inputs and a number of outputs. This leads to 702 where a user may define and initialize a population. Then, at 716, a user may define fitness and a specific problem. Steps 702 and 716 lead to calculating fitness for each member of the initialized population at 704. At 706, does the best member meet the fitness requirements? If Yes at 708, the best member is output at 710. If No at 720, the tournament or roulette process 724 begins by asking at 722, is the child population full? If Yes at 718, there is a return to fitness calculation 704. If No, then, two fit parents are selected at 730 and a roulette or tournament selection begins at 712 and is input to 730 for the selection process. After parents are selected, a crossover is performed at 732 if needed. Also, a mutation is performed at 728 if needed. Crossover 732 and/or mutation 728 (if needed) may be performed based on a predetermined probability of occurrence 734 of one or the other. At 726, children are added to the child population at 726 and the crossover/mutation process 724 begins again at 722 asking if the child population is full which continues until the answer is Yes at 718. FIG. 7B provides a blow-up of the crossover/mutation process 724 of FIG. 7A.

Referring now to FIG. 7B, a parent population 736 is input in crossover/mutation process 724 of evolutionary optimization (EO). A fitness calculation 738 for one of control, anomaly detection, classification or other application 735 of a NIDA/DANNA is applied to the parent population resulting in a plurality of networks 737, for example, networks 740 which may be eight in number. Of these, selected parents 742 result (for example, 1 and 3). Crossover 744 is applied such that no child is a clone of a parent. Two selected parents 742 result in two different children with crossover 744. After crossover 744, mutation 746 may be applied and a resulting child population 748 thus results.

In the crossover operation 744, the average desired firing rate of the parents is taken to be the desired firing rate in both children produced. A new mutation 746 that sets the desired firing rate to a randomly selected value between zero and the number of neurons in the network is added to the mutation operation. The parameters of the evolutionary algorithm are given in the Table 2. Mutation Types and Rates are provided in Table 3.

TABLE 2 Evolutionary Algorithm Parameters Parameter Value Population size 500 Mutation rate 0.9 Crossover rate 0.9 Tournament size 20

TABLE 3 Mutation Types and Rates Mutation Type Mutation Rate Change sign of the weight of a randomly selected (RS) .267 synapse Randomly change the weight of a RS synapse .267 Add a synapse between two RS neurons that are not .133 already connected Delete a RS selected synapse .133 Add a neuron at a RS position .027 Delete a RS neuron .013 Change the threshold of a RS neuron .027 Change the desired firing rate to a RS value between 0 .133 and the number of neurons

An array of programmable adaptive neuromorphic elements may use a field programmable gate array FPGA and the Dynamic Adaptive Neural Network Array or DANNA component models. A VLSI (application specific integrated circuit (ASIC)) may also be used. Embodiments of a DANNA will now be described with reference to FIG. 9A through FIG. 19. The capacity, logic structures, functions and layout of Xilinx Virtex-7 FPGAs (a Xilinx Zing FPGA with an ARM processor may also be used to construct a DANNA with programmed control) provide the potential to support useful array sizes, up to 10,000 (or more) programmable elements. Programming, control and I/O interfaces are described to enable the creation of a target neural network and the monitoring of its operation. Finally, the potential performance of an FPGA-based DANNA is discussed with a VLSI-based DANNA implementation.

A model of a neuron inspired by the Hodgkin-Huxley model may comprise operating components such as a neuron charge accumulator, a threshold and a refractory period, and may also comprise a synaptic propagation delay and a weight. This neuron element may introduce dynamic behaviors in the network, serving as memory and influencing system dynamics. Unlike most proposed ANN architectures, but similar to natural neural processes, these dynamic effects may be distributed throughout the network, and are directly influenced in the present ANNs by the evolutionary programming methods utilized to construct and adapt the ANNs for specific purposes such as control, anomaly detection and classification.

The primary function of a DANNA neuron element (which may also serve as a synapse to be discussed further herein) is to accumulate “charge” by adding the “weights” of firing inputs from connected synapses to its existing charge level until that level reaches a programmable threshold level. Each neuron has an independently programmable threshold 901 received from a threshold register (not shown). Referring to one of FIG. 9A or 9B, the depicted circuit element is advantageous in that it may comprise either one of a neuron and a synapse. The neuron will be discussed first. Threshold input 901, indicated by an asterisk or star *, receives a threshold value stored in a register not shown and provides that value to Accum (Accumulator) input C and to Comparator 917 input B. Inputs 0-8 (8 bits in FIG. 9A, 0-15 or 16 bits in FIG. 9B) to MUX/Select 910 are selected by Input_Sel input (3 bits, FIG. 9A; 4 bits FIG. 9B). An Accum, Inc/Dec Weight, Neuron/Synapse register (not shown) stores whether the element is a neuron or synapse and provides an increment/decrement value to CTRL input of Accumulator 915. Meanwhile the charge value stored in Latch is output by an 8 bit lead to input A of Accum/Latch 919 for comparison with Threshold at comparator 917. When the threshold is exceeded at 917 and given clock Acquire_Clk a Fire signal is output and latch 921 outputs Element Output. When the threshold is reached and the element is a neuron, if the neuron is not in its refractory period, the neuron fires, and the neuron's charge is reset to a bias level, dependent on the design parameters for the network. If the neuron is within its refractory period defined by an LTD/LTP Refrac period input from a register not shown to CNT input 904 of 4-bit counter 935, then the neuron maintains its charge but does not fire. An LTD/LTP state machine receiving an Element_Fire signal from above helps determine if Inc/Dec Weight output to CTRL input of 919 decide whether to fire or continue accumulating. Thus, a neuron can accumulate charge during its refractory period (input 904), but it cannot fire during this period. As soon as a neuron fires, it enters its refractory period. The refractory period for all neurons is preferably a constant value set for a given application or operational characteristic. One utility of the refractory period is to limit the maximum firing rate of neurons which typically limits energy consumption by the neuron element of a DANNA.

We have chosen a weighted-sum threshold activation function for the neuron charge given its implementation simplicity and functionality, but other activation functions could be implemented (e.g. linear, sigmoid or Gaussian).

The neuron charge function H_(kj)(t) can be expressed as:

${H_{kj}(t)} = {{\sum\limits_{i = 1}^{N}\; {{w_{i}(t)}{x_{i}(t)}}} + {H_{kj}\left( {t - 1} \right)}}$

where kj is the location address in the 2-dimensional array (kjl in a 3-dimensional array), N is the number of neuron inputs, w_(i) is the weight of input x_(i) and t is the discrete sample time for network sequencing. Weights can be negative or positive discrete values with minimum and maximum limits set by the functional requirements of the target applications. For this implementation we chose to use signed 8−bit weights (−128 to +127) and a 9-bit charge accumulator.

The neuron activation function α_(kj)(t) (the point at which a neuron will fire its output) can be expressed as:

${a_{kj}(t)} = {{f\left( {H_{kj}(t)} \right)} = \left\{ \begin{matrix} 1 & {if} & {{H_{kj}(t)} \geq {\theta (t)}} \\ 0 & {if} & {{H_{kj}(t)} < {\theta (t)}} \end{matrix} \right.}$

where θ is the neuron's programmable threshold. When the neuron's charge reaches its threshold level the charge of the neuron is reset to a predetermined bias level before starting a new charge accumulation phase. The bias value is the same for all neurons in the network in the current design. For this implementation the thresholds are limited to binary values from 0 to +127. This neuron model follows to some extent a computational model for a neuron proposed by Rosenblatt (Rosenblatt 1958).

Additional features of our neuron model are the number of inputs/outputs and its firing refractory period. The implementation of FIG. 9A supports 8 input/output (I/O) ports connecting to nearest neighbor elements. The implementation of FIG. 9B supports 16 input/output ports to Input Data Mux/Select 910 selected by Input Sel input as a 4 bit select input to Mux (3 bit select in FIG. 9A for 8 input/output ports). Note that each port can be an input and/or an output, and each port that is enabled to accept an input used must connect to an element (feeding the neuron) programmed as a synapse. Input port sampling is done sequentially by Input Sel and must be randomized to avoid having a single synapse dominate the interactions with the neuron, and to avoid specified, undesirable learning behaviors such as crediting LTP/LTD actions to a preferred or single synapse. This is done by having the first port address sampled in a network cycle be random and each subsequent port address be in sequence from the first address (such as binary ordering by port number).

The neuron refractory period defined at 904 is the amount of time, measured in network cycles, which a neuron must hold off firing from a previous firing condition. We have set the neuron refractory period to one network cycle, meaning if the input firing rate and weights are sufficiently high, a neuron can fire on every network cycle. If the firing rate for neurons needs to be programmable, an alternate design may implement a programmable firing refractory period that may be input 904.

A model for neurons of a DANNA allows them to be either input neurons or internal neurons (not connected as input neurons or output neurons in the DANNA). Input neurons may be placed along specified edges of an array to facilitate routing. Neurons may be connected to other neurons via one or more synapses. Synapses are directed (later shown as arrows), so each neuron has one or a set of synapses to other neurons and a set of synapses from other neurons.

As indicated above the element of FIG. 9A or FIG. 9B may be selected to comprise a synapse in the alternative to serving as a neuron. Synapses may also connect to other synapses, for example, in order to implement delays in excess of the capability of a single synapse, and to implement longer signal path lengths between neurons they connect. Synapses are defined by the neurons they connect; each synapse may be directed from one neuron to another neuron. Each synapse circuit element represents the distance between two neurons and the weight (or strength) of the synaptic connection. The distance between the two neurons is represented as a delay, implemented using a first-in/first-out (FIFO) shift register clocked at the network cycle rate, and determines how long it takes for charge to travel along the synapse where the charge value is stored and fed to Accum, Inc/Dec Weight 902 a. Also note that Synapse_Distance is fed at input 902 b Synapse_Distance, Neuron/Synapse. The weight of the synaptic connection determines how much charge arrives at the second neuron after the first neuron fires. This network model does not implement the concept of myelination, but myelination is equivalent to a reduction of the (programmable) delay. Alternatively, a hardware implementation may be used, for example, a clock divider circuit for changing delay or by connecting synapses together of programmed delay to double delay. If two synapses are each of length d, then it takes the same amount of time (delay) for charge to travel from one end of each synapse to the other. Synapses of a DANNA capture selected features of both axons and synapses found in biological neural networks.

A primary function of a DANNA synapse circuit element is to adapt and transmit a weighted firing signal based on: 1) the firing rate of its input neuron, 2) the firing conditions of its output neuron and 3) its programmable distance which represents the effective length of the synapse. Again, note inputs Accum, Inc/Dec Weight, Neuron/Synapse 902 a and Synapse_Distance, Neuron/Synapse 902 b. Two of the unique characteristics of our synapse model are: 1) the weight value held by the synapse can automatically potentiate (long-term potentiation, or LTP) or depress (long-term depression, or LTD) (Inc/Dec) depending on the firing condition of its output neuron and 2) the ability to store a string of firing events in its “distance FIFO” (Synapse_Distance input 902 b) to simulate a synapse transmitting a set of firing events down its length. Note we are preferably implementing a synapse's length into a representative number of discrete time periods using a programmable shift register.

A synapse can have one (out of eight) I/O ports (FIG. 9A or one of 16 in FIG. 9B) enabled as an input and one (out of eight, FIG. 9A; out of 16, FIG. 9B) I/O ports enabled as an output (Input Fire Mux/Select 920). When a synapse receives a firing event from an input neuron, it places this event on its distance FIFO 930. Preferably, multiple input events received during each element clock cycle (906 a) are OR'ed together to create a single input event to the FIFO register. The distance FIFO 930 is a programmable shift register that can store from 1 to 256 firing events (one per network cycle programmed as the “distance” of the synapse). When each firing event reaches the output of the distance FIFO 930, the present weight value stored in the synapse is transmitted as a firing event on its output port (Element Fire).

As mentioned, the synapse weight will automatically adapt based on its firing condition and the firing response of its output neuron. LTP and LTD occur in biological brains; it is speculated that they play a major role in learning. The adaptive synapse weight function, w_(kj)(t), can be expressed as follows:

if  S_(kj)(t) = 1, then ${w_{kj}\left( {t + 1} \right)} = \left\{ \begin{matrix} {{{w_{kj}(t)} + {{LTD}\mspace{14mu} {if}\mspace{14mu} {a_{neuron}\left( t_{s} \right)}}} = 1} \\ {{{{w_{kj}(t)} + {{LTP}\mspace{14mu} {if}\mspace{14mu} {a_{neuron}\left( t_{s} \right)}}} = {{0\mspace{14mu} {and}\mspace{11mu} {a_{neuron}\left( {t_{s} + 1} \right)}} = 1}}\;} \\ {{{w_{kj}(t)}\mspace{14mu} {if}\mspace{14mu} {a_{neuron}\left( t_{s} \right)}} = {{0\mspace{14mu} {and}\mspace{14mu} {a_{neuron}\left( {t_{s} + 1} \right)}} = 0}} \end{matrix} \right.$

where S_(kj)(t) is the synapse output firing condition, a_(neuron)(t_(s)) is the activation function or firing condition of the neuron connected to the synapse's output at the time during the network cycle it samples the synapse output, LTD is the “long term depression” value for the synapse, and LTP is the “long term potentiation” value for the synapse. Note that (t_(s)+1) is the next input sample cycle after the neuron has sampled the synapse output; given eight inputs, the network cycle is divided into eight input sample cycles.

For a preferred implementation, the LTP and LTD values are set at +1 and −1, respectively. Therefore, a synapse's weight is increased by one if it causes its output neuron to fire and is decreased by one if it fires when its output neuron is already firing (Accum, Inc/Dec Weight, Neuron/Synapse 902 a). It is unchanged in all other conditions.

Finally, a synapse has a programmable LTP/LTD refractory period (LTD/LTP Refrac Period 904). This programmable value (ranging from 0 to 15) represents the number of network cycles a synapse must wait from its last weight potentiation or depression before it can adjust its weight again. This value is input to Cnt input of 4-Bit Counter 935. This function limits the rate of potentiation/depression of a synapse's weight. All potentiation and/or depression conditions experienced during the LTP/LTD refractory period are ignored; they have no effect on the synapse weight. The utility of the LTP/LTD refractory period is to adjust the relative rates of change of synaptic weights and neuronal firing activity. The LTP/LTD refractory period and the neuron refractory period can be used in combination.

An array element shown in FIG. 9A or FIG. 9B implements all the functions necessary to support its operation as either a neuron or a synapse where FIG. 9A portrays an eight input of 8 bits each embodiment and FIG. 9B portrays a sixteen input embodiment of 8 bits each to Mux/Latch 910. To minimize the physical implementation size of the array element, as many functional components as possible are used to support portions of each neuromorphic function. To maximize performance and minimize size, we, by preference, may use a simple state-machine design (LTD/LTP State Machine) and avoid the use of digital signal processors, floating-point units, arithmetic-logic units, memory arrays and other common microprocessor units. However, a more complex state machine and further processing may be implemented in alternative embodiments (for example, Xilinx Zinq).

The states used to sequence the array element are defined as follows: 1) Select an input port (1 of 8 or 1 of 16) and 2) acquire input fire condition (Note: all 8/16 ports of an element are sampled (or not) during a single network cycle). (Inputs to neurons, for example, may be selectively enabled or ignored if they are not to fire (on a neuron by neuron basis). Next, check the fire condition of the element assigned to the output port (used to determine LTD/LTP if the element is configured as a synapse). Load the synapse FIFO 930 with the input fire condition if the element is a synapse. 3) Accumulate the acquired input weight with the current charge state at accumulator 915, 919 and compare the accumulated charge with the programmed threshold at comparator 917 if the element is configured as a neuron. The accumulator 915, 919 holds the LTD/LTP weight if the element is a synapse. Depress or potentiate synapse the weight (Inc/Dec Weight 902 a) based on the firing condition of the element assigned to the output port. 4) Fire the output and reset the accumulator 915, 919 to the bias value if the charge≧the threshold if the element is a neuron and optionally if the neuron is not refractive (for refractory periods>1). Fire the output if a fire event is at the output of the synapse FIFO 930 if the element is a synapse.

The “Fire Output” and “Acquire Input” states may overlap, reducing the state machine to two states. A network cycle consists of eight (sixteen) element cycles, and the element may sample eight (FIG. 9B, sixteen) inputs during a single network cycle. Therefore, in the example of FIG. 9A, it takes eight (FIG. 9B, sixteen) element cycles to complete one network cycle. The following list of functional components is implemented in the array element; these components are illustrated in the block diagram of the element in FIG. 9A for 8 inputs and FIG. 9B for 16 inputs.

Referring now to FIG. 9A, the following types of programmable registers are used in FIG. 9A: An 8-bit Threshold/Weight Register (stores threshold for neuron, or weight for synapse) and is an input 901; an 8-bit Synapse Distance Register (synapse mode only) 930 receives inputs IN from Input Fire Mux/Select 920, Net_Clk 906 b and Synapse_Distance 902 b; an 8-bit Input Enable Register 910 receives 8 bit inputs 0-7 (FIG. 9A) or 0-15 (FIG. 9B) and Input_Sel as well as CLK from Acquire_Clk 907 b; a 4-bit Mode/Output Select Register (Neuron/Synapse; 3-bit (FIG. 9B, 4-bit) output port select 903 if a synapse, which is used to determine which connected elements output should be monitored for LTD/LTP), and a 4-bit LTD/LTP Refractory Period Register (synapse mode only) (input 904 to 4-bit counter 935). Note that a star * in the drawings FIGS. 9A and 9B is used to designate such registers as inputs. A clock diagram will be described with reference to FIG. 10C.

The 8×9-bit I/O port 910, 920 will now be described with reference to FIG. 9A. Each port includes an 8-bit uni-directional I/O data interface to communicate “weights” to 910 and a “lire” signal to 920 respectively. An I/O can communicate a “fire event” from a neuron to a synapse or a “weight” from a synapse to a neuron. The 8-to-1 input port multiplexer and latch 910, 920 is further described as follows. Each input port is 9-bits wide (1-bit “fire” to 920 and 8-bit “weight” signals to 910). The network provides global input select signals (Inp_Sel) to support sequencing through all connected inputs. A pseudo-random number generator may be used to randomize the input sampling sequence during each network cycle. (See FIG. 10A, Global Clocks and Input Selects 1005 and FIG. 10C) which may be implemented in any known manner depending on choice of clock rate and divided as necessary to provide select and acquire and the like for the desired network).

The 9-bit accumulator (adder 915, comparator 917 and latch 919) will now be described. This holds and calculates “charge” for a neuron or “weight” for a synapse. Comparator 917 also compares “charge” to “threshold” for a neuron. The accumulator 915 accumulates input firings from all enabled inputs to the neuron (inputs enabled selectively from 0 to 8 (FIG. 9A) or 0 to 15 (FIG. 9B). The weight of each input firing event is stored and added to the “charge” in the order it is sampled. Each weight is an 8-bit signed integer. When an element is a synapse, its weight will be depressed or potentiated, by adding −1 or +1 respectively, (Inc/Dec Weight 902 a) depending on the effect the synapse firing event has on its connected neuron.

The 8-bit output register 921 to hold output communications to connected array elements (the “threshold” when configured as a neuron and the “weight” when configured as a synapse) will now be described. The output register value (Element Output) is driven onto the output port during a “firing event” and held active for one network cycle. At all other times the output is zero.

A Synapse Distance FIFO 930 stores input firing events to a synapse and maintains the firing delays between those events. This is implemented via a 1-bit wide×256 entry shift register 930. The Synapse Distance Register 930 selects the appropriate “tap” off the event shift register to implement the “distance” (a delay) associated with the configured synapse. Equivalently, a signal injection point may be selected.

A 4-bit counter and register (or 16-bit shift register) 935 with programmable length will now be described. This holds and implements the LTP/LTD refractory period for a synapse. A global programmable refractory period register (output designated LTD/LTP Refrac Period 904) is used to drive a 4-bit refractory period “length” to all elements.

Clock inputs are created by a network clocking circuit and distributed to manage fan-out and minimize clock skew. Fan-out implements a way to have more than 8 (or 16 or more) input/outputs as will be discussed further herein. These include a Global Network Clock (Net_Clk) 906 a and 906 b, also shown as signal G_N_C in FIG. 10C, an Acquire/Fire Clock (Acquire_Clk) 907 a and 907 h, also shown as A_F_C in FIG. 10C, and an Accumulate Clock (Accum_Clk) 908, also shown as A_C in FIG. 10C, provides accumulated clock time. The Global Network Clock 1005 sets the network cycle time. Acquire/Fire Clock 907 controls the element cycle time and Accumulate Clock 908 enables the accumulator latch 919 input CLK to perform two operations every element cycle (load and accumulate). Signal line and device names are chosen as arbitrary and, when used in the claims, such signal line and device names are intended to refer to any such signal line and device name that may be used to perform a similar function, in a similar way to accomplish a similar result. For example, accumulate clock refers to a function of accumulating clock time in time units measured according to the application as real time or selected time units that may be intentionally slowed, for example, to study a particular event in a slow motion visualization of a neural network array event process.

A Programming/monitoring interface (shown as a PCIe Interface) 1010 of FIG. 10A (or other known interface technology or method may be used) enables register reads/writes from/to the external interface. In the current implementation, each element in the array is directly addressed via a multiplexed 8-bit address/data port (which supports a 16-bit global element address and an 8-bit data port), a 3-bit element register select, a read/write signal, a strobe, a clock, a Run/Halt signal and Reset (16 signals total).

FIG. 9B is a bock diagram very similar to FIG. 9A except providing for sixteen element inputs of eight bits each and so a four bit (I of 16) select. It is not believed necessary to discuss FIG. 9B in great detail. The element code appended hereto is for the sixteen bit element and associated registers shown in FIG. 9B (which like FIG. 9A may be a neuron or a synapse).

Before discussing FIG. 9C and referring to FIG. 10A, there is shown a high-level block diagram of the array of elements of FIG. 9A or 9B and the programmatic and control functional elements. This may be modified in alternative implementations to provide additional control and monitoring functions. The element array may be structured as a 2-dimensional array that is k elements wide by j elements high (elements being one of a synapse and a neuron). Each circuit element connects to eight (16 or 24 or 32 . . . ) of its nearest neighbor elements (directly above, below, to the right and left, and diagonal), except for elements on the edge of the array, which have a limited number of connections. Some of the edge elements are used as inputs/outputs to external signals and devices and are neuron elements. One may also place static “pass-thru” elements (990, FIG. 9C) throughout the DANNA array. These pass-thru elements provide a static connection between corresponding horizontally, vertically and diagonally connected ports. The pass-thru element provides additional flexibility to the network configuration software, allowing it to avoid creating chains of connected elements that would otherwise block access to other parts of the array.

A pass-thru element is shown in FIG. 9C having 8 inputs from 8 different outputs for the array element of FIG. 9A. A pass-thru (or pass-through) element or cell allows signals to cross paths so that one pathway does not block another signal. As per FIG. 9A, an eight I/O element may be shown as per FIG. 9C. Any input shown in FIG. 9A (the eight input element) may receive an input as an output from any of eight connected elements. Each element (in this figure called a pass-thru element or “cell”) may receive an output from eight others without blocking another signal. So starting from 12:00 on the dial, input 0 of cell/element 910 may connect to I/O 4 of Cell X, Y+1. Input 1 of cell/element 910 may connect to I/O 5 of cell/element X+1, Y+1 and so on to I/O 7 at 10:00 on element 910. I/o's may be sequentially addressed to prevent signal blocking generally and, in particular, in a static pass-thru element. Other numbering schemes may be used in FIG. 9C and the numbering scheme shown is merely exemplary of all possibilities.

Referring again to FIG. 10A, in one embodiment, the FPGA DANNA array of circuit elements connects to, for example, a PCIe interface 1010 that is used for external programming and adaptive “learning” algorithms that may monitor and control the configuration and characteristics of the network and may have array circuit elements 1021, 1023, 1031, and 1033 that may be located on an edge of the array and may have external inputs or outputs. Array elements, including 1021, 1023, 1031, and 1033 may preferably also have inputs or outputs that are internal to the array. Array circuit elements and components thereof may be digital or analog, but as will be seen in the discussions of FIGS. 9A and 9B, the FPGA implementation of a circuit element selectively being a neuron and a synapse may comprise digital circuit components such as registers of digital data. Analog circuit elements that may be used in constructing a circuit element of an array (besides the implementations shown in FIGS. 9A and 9B by way of example) include a memristor, a capacitor, inductive device such as a relay, an optic device, a magnetic device and the like which may implement, for example, a memory or storage. “Analog signal storage device” as used in the specification and claims shall mean any analog storage device that is known in the art including but not limited to memristor, phase change memory, optical storage, capacitive storage, inductive storage (e.g. a relay), magnetic storage or other known analog memory device.”

Other interfaces may be used as indicated in FIG. 10B. Interface and control 1040, such as a FMC bus, a serial or parallel communication interface such as a Universal Serial Bus (USB) interface using, for example, the USB 2.0, 3.0, or newer standard, a Bluetooth interface, an interface using one or more pairs of conductors, or a network interface using, for example, copper wiring such as CAT6 {or CAT5e, such as are used for Ethernet, Fast Ethernet, or Gigabit Ethernet, or 10G Ethernet, Myrinet, and Infiniband, fiber optic such as OC-3, OC-12, OC-48, ATM, or a point-to-point data transfer protocol using, for example, single-mode or multi-mode fiber optic cable, a HDMI interface, or a wireless network interface including circuit-switched and packet data cellular such as 3G, 4G, 4G LTE, and enhanced protocols, Wi-Fi such as 802.11, as exemplified by the 802.11a/b/g/n/ac variants and future proposals and standards, and industrial automation, communication, and/or control protocols such as, by example, Modbus and its variants, Controller Area Network (e.g., CANopen), Ethernet/IP, and specialized protocols such as Z-Wave and ZigBee. Additional devices may be used to implement an interface such as a computer or processor known in the art, where the processor, or a processor core, may be co-resident with a device or devices implementing one or more DANNA(s) on a common semiconductor substrate. For example, a DANNA may be implemented using one or more FPGA, VLSI or ASIC devices, in any combination, and may include a mixture of analog and digital components, may have an interface to a first special purpose processor, which may be a computer and which may optionally be resident on the same semiconductor substrate as a DANNA, running special purpose software to provide for transactions, including command and data transfers, between the DANNA (or multiple DANNAs) and a second special purpose processor. The second special purpose processor may also be a computer and may optionally be remote from the first special purpose processor, such that the second special purpose processor controls the operation of the DANNA and optionally may configure the DANNA and perform optimization of one or more artificial neural networks configured on or in the DANNA special purpose software. By example, any of the interfaces or interface technologies or standards listed above may be utilized to implement an interface between any two or more special purpose processors and/or between a special purpose processor and a device or devices that implement one or more DANNA(s). There may be multiple first special purpose processors and multiple DANNAs implemented on or in one or multiple FPGA/VLSI/ASIC devices or combinations. Each first special purpose processor may execute special purpose software that implements a capability to facilitate transactions between the DANNAs and the second special purpose processor. Also, there may be more than one second special purpose processor that operates in a coordinated manner using interfaces and communications protocols known in the art to implement a solution to at least one of a control, detection, or classification application. The interface 1040 provides for communication between the DANNA and a control and, optionally, optimizing device 1060, which is optional and may not be present in stand-alone implementations.

Each element may sample eight of its input ports of FIG. 9A (or 16 of FIG. 9B) within a network cycle. This is accomplished using a global input select function. A 63-bit linear-feedback shift register (LFSR) is used with a loadable 3-bit counter to generate random starting address sequences for the input selects which guarantee that the first element selected during each network cycle is randomly chosen with roughly uniform probability. Eight element-inputs (FIG. 9A circuit element) may be sequentially sampled beginning with the randomly chosen one within a single network cycle. Randomization of input sampling is important to prevent the domination by one input of the behavior of a neuron.

A design feature of the element array is the numbering scheme used for the I/O ports. Connected I/O ports on adjacent network elements may have the same port number to facilitate implementation of the synapse's LTD/LTP function. The element I/O port number scheme used is shown in FIG. 10.

The Xilinx Vivado™ Design Suite was used for the design, implementation, simulation and layout of the DANNA element array. VHDL was used as the description language for all designed components. The code is attached hereto for the several components of each circuit element. We targeted the Virtex-7 series of Xilinx FPGAs. The main logic resource used on the Xilinx 7-series FPGAs is the “configuration logic block” or CLB. Each CLB contains two Slices, which each have four 6-input “look-up tables” (LUTs), eight flip-flops and arithmetic carry logic. There is also logic to implement wide multiplexers and long shift registers. Other tools and hardware may be used such as Xilinx Zing and Alterra FPGA by way of example.

An element implementation may require, for example, 84 LUTs and 64 flip-flops. One may fit the element in a tightly arranged 28 Slices or 14 CLBs using the Vivado floor planning and placement tools. Note that none of the on-chip digital signal processors (DSPs) or Distributed Ram Blocks was used in the element design as can be seen in either FIG. 9A or 9B.

Element simulations of DANNA and construction of elements, verify full functionality for both neuron and synapse modes of a circuit element of either FIG. 9A or 9B. A target clock rate for the network may be 1 MHz and 8 MHz for the element (sample rate for the inputs). Further timing simulations showed we may clock the network at 8 MHz and the element at 64 MHz. A 10 MHz network clock and 80 MHz element clock rate are achievable (if not higher rates). The higher clock rates are important because evolutionary optimization (EO) is typically used to design a DANNA for a specific implementation and application. EO ideally configures multiple DANNAs, simulation or execution of them against the application (for example, for signal detection or classification, or to control a (possibly simulated) physical object's behavior, and a limiting factor in the optimization may be execution and evaluation of the performance of individual DANNAs. Higher clock rates translate directly to more rapid convergence of the EO design steps.

The global functions were implemented and tested using the same design tools and simulation models as the element. This included the Clocks, Input Select, PCIe, programming interface, and programmable registers for network control and LTD/LTP refractory period. The PCIe and programming interface took the most logic to implement. By reducing the PCIe interface 1010 to a single lane (1×), this significantly reduced the logic required to interface the array to an external computer.

A final design was configured, loaded and tested on two different Xilinx evaluation boards: the VC709 evaluation board featuring the XC7VX690T FPGA and the VC707 evaluation board featuring the XC7VX485T. The 485T FPGA has 75,900 Slices, and the 690T FPGA has 108,300 Slices. An array of approximately 2500 elements was placed on the 485T FPGA and an array of approximately 3500 elements on the 690T FPGA. Using Xilinx's largest Virtex-7 FPGA, the XC7V2000T, an element array of approximately 10,000 elements may be constructed. With the array sizes achieved, many solutions needing a neural network array (DANNA) can be supported.

We now provide exemplary element VHDL code (without copy restriction as defined below) for the sixteen bit input array of FIG. 9B. Note that the following code applies to identified elements above, for example, Signals for 8×8 input mux and input control and so on:

Now, referring to FIG. 10B, a DANNA system of FIG. 10A will be described comprising an optimizing device and a neuromorphic device. A DANNA may be implemented that is comprised of one or more subsystems. If two or more subsystems are present, these subsystems can communicate. One preferred embodiment of a subsystem is comprised of two computational elements. The first computational element is comprised of at least one processing circuit or device called an element or cell, and the first computational element will be referred to herein as a neuromorphic device. The second computational element implements an evolutionary optimization algorithm that can modify the operation or configuration of the first computational element in response to measurements of the performance of the first computational element. The second computational element will be referred to herein as an optimizing device. The first and second computational elements may be two physical devices that can communicate, different portions of the same device, such as an integrated circuit, field programmable gate array (FPGA) or application-specific integrated circuit (ASIC), or implemented by one or more physical devices, such as with a general purpose computer or processor such as a server, a desktop workstation, a laptop, or an Intel or AMD processor, a networked collection of computers, or supercomputer using software. An optimizing device may be interfaced to a DANNA/NIDA neuromorphic device.

A parallelization of such optimizing device and neuromorphic device combinations may be constructed. The devices can communicate using communications hardware or software components, as depicted in the diagram, where the communications can employ communications protocols such as TCP or UDP, wireless or wired networks such as Ethernet, Gigabit Ethernet, WiFi, WiMax, ATM and 3G or 4G technologies such as 4G LTE, hardware communications structures such as PCIe, serial or parallel communications channels which may be electrical or optical, and may employ either digital or analog communications methods and/or devices, as are well known in the fields of electrical engineering and computer engineering. It is preferred that embodiments having more than one subsystem coordinate the operation of those subsystems to achieve a common purpose, such as the control of a physical or virtual (such as software) system, classification of signals, which may be indexed by either time or frequency, including signals obtained using radar or sonar, and signals that represent data indexed by two or three dimensions such as medical signals obtained using CAT, MRI, or PET scanning technologies or a combination thereof and medical signals obtained using EEG, MEG, or chemical sensing technologies, or a combination of any of these.

It is not required that the subsystems of an embodiment have common goals. For example, a subsystem's goal may be the improvement or stabilization of the behavior of a second subsystem, while the second subsystem's goal may be the control of an external process, or the classification of one or more signals, or the identification of characteristics of at least one signal. As a second example, a goal of a subsystem can be affective, such as the promotion of bonding of other subsystems to operate as a team to achieve one or more goals, or such as the control or influence of the seeking behavior of a second subsystem whose goal is the exploration of its environment, as in a robotic or unmanned vehicle. A third example of an affective goal of a subsystem is the control or influence of a fear response in a second subsystem to cause the second subsystem to avoid unnecessary risk or unacceptable risk of damage or destruction, as in the control of an unmanned vehicle in a hostile environment. A fourth example of an affective goal of a subsystem is the control or influence of a rage response in a second subsystem, as in being able to trigger defensive or offensive actions in an autonomous system. A fifth example of an affective goal is to control the behavior of an automated process upon prediction of a component failure.

The optimizing element may be further divided into two sub-elements, an evolutionary optimization component (EO component) and a performance measurement component where the first sub-element implements the evolutionary optimization algorithm, and the second sub-element implements one or more measurements of the performance of the first computational-element. Either the first or second computational element may be comprised of multiple circuits or devices as shown below. For example, the second computational element may be one or more general purpose computer processors such as Intel or AMD processors, and each processor may have one or more computational cores and be capable of executing multiple threads, either simultaneously using multiple cores or by time-slicing or using other methods that are well-known in the field of computer engineering.

The neuromorphic device of the first computational element may comprise multiple cells/elements as shown FIG. 10B, where each cell/element may implement functionality characteristic or similar to that observed of a biological neuron or synapse. The figure shows, by way of example, cells that are organized in a two-dimensional array, but other organizations can be used such as a linear, ordered, or indexed array of cells, which may be in one, two, or three dimensions, or the cells may be virtual components existing in a system implemented in software.

In FIG. 10B, cells/elements of DANNA/NIDA 1090 may also be designed to implement other functionalities. For example, a call may be designed to implement the functionalities characteristic or similar to that of a place node or a transition node or an arc of a Petri net. In this case the functionalities may be extended to include different types of place nodes, transition nodes, and arcs, for example by implementing both enabling and inhibiting arcs that enable a transition node to fire and inhibit a transition node from firing, respectively. Another type of extension is the optional inclusion of additional functionality or parameters in the functionality of a place or a transition. For example, a place may be required to cause any Petri net tokens to remain within a place for a specified time period, which may be a random time characterized by a probability density or distribution that may be characterized by one or more statistical parameters. As an additional example, a transition may be required to cause a function of its input tokens, or of parameters or variables associated with its input tokens, to satisfy a mathematical relationship before the transition can fire or be enabled.

Still referring to FIG. 10B, in a preferred embodiment the cells can be programmed or configured by a device or function implemented either internal to or external to the neuromorphic device. FIG. 10B illustrates an interface and control structure 1040 that may be accessed by an external device or process 1080 such as the optimizing device using the communications pathway (for example, mod and demod 1070), which may consist of signal lines or pins on a physical device to which other components may be connected. In this embodiment, the interface and control structure 1040 is interfaced with or communicates with the cells/elements or configuration devices (illustrated in the figure as the configuration structure 1050), which may include memory elements and may be either a part of or separate from the cells/elements. A function of the interface and control structure 1040 is to effect the configuration of the cells/elements into a neuromorphic network, such as a network of neurons and synapses described by a neural network or a network of place and transition nodes and arcs described by a Petri net.

Where the cells of the neuromorphic device of FIG. 10B may implement functionality characteristic or similar to that observed of a biological neuron or synapse, when it is clear from the context, the terms “neuron” and “synapse” will be used for either circuitry, devices or software (NIDA) that implement these functionalities, or a biological neuron and synapse. In a first preferred embodiment each cell/element can be configured or programmed to implement either a neuron or synapse as described above, and such configuration or programming can be changed by an action of the optimizing element. In a second preferred embodiment, each cell/element can be configured or programmed to implement either a place or a transition associated with a Petri net, and such configuration or programming can be changed by an action of the optimizing element. Optionally, the optimizing element may initialize parameter values or state information or variables associated with a cell/element.

In these preferred embodiments the optimizing device can configure two or more cells by specifying connections between them, such connections being signal pathways or devices that allow information, which may be represented or transmitted by digital (binary, typically represented as zero and one, true and false, or by two symbols), analog (having continuous value, optionally within some range of values), or discrete (having one of a set of multiple and distinct values that may be represented by a set of integers or symbols) values. Each signal pathway can be designed and implemented to transmit or convey information, as one or more values, either serially or in parallel, as is known in the art from one or more cells to one or more cells, which may but do not have to be the same. The connectivity between cells that may be formed by the connections specified by the second computational element can be called “programming”, “initializing”, or “configuring” the neuromorphic device or circuit, and the resulting specification and implementation of the configurations of the cells, of the optional parameters, states, or variables associated with one or more of the cells, and of the connectivity between cells can be called the “configuration” or “program” of the neuromorphic device or circuit.

In a preferred embodiment, the cells/elements of the neuromorphic device operate in an asynchronous or discrete-event manner, meaning that events or actions occur at times which conditions are met within one or more cells to cause the creation of an event at that time. In practice the cells/elements will typically operate in a synchronous or clocked manner, meaning that a clock signal exists, which preferably has a short time period relative to the rate at which external signals received or generated by the neuromorphic device change values, and that events occur at times that are coincident or nearly coincident (allowing for signal propagation, logic gate, or other device delays) with transitions of the clock signal's values. More than one clock signal may exist and be used or generated by the neuromorphic device, as is well known in the art of electric engineering and computer engineering, and these clock signals are typically related by phase offsets and/or the division of a common clock frequency by positive integers.

In a preferred embodiment that utilizes cells/elements that implement neurons and synapses, cells that are configured to implement synapses are used to implement connections between cells/elements that are configured to implement neurons, and possibly between those neuron cells and external components or other components within the neuromorphic device, which may, without limitation and by example, be a counter, a device to select one of a set of values, which may be digital, analog, or discrete, a demodulator that produces a digital or analog signal that depends upon a signal received from a cell configured as a neuron, or a modulator that converts a digital or analog signal to a signal that can be transmitted to a cell configured as a neuron. Thus, a cell configured as a synapse has one or more inputs, which are each connected to a cell, and has one or more outputs, which are each connected to a cell. In both cases the cells connected to the cell configured as a synapse may be configured as either a neuron or a synapse. This allows multiple cells configured as synapses to transmit information along pathways within the neuromorphic device or circuit. If the embodiment utilizes software or a combination of software and hardware to implement a neural network, then the components that translate and transmit or receive signals to/from external devices of other components within the neuromorphic device may be implemented in software (NIDA) or a combination of software (NIDA) and hardware.

In a preferred embodiment that utilizes cells/elements that implement the place and transition nodes and the edges of Petri nets, cells that are configured to implement edges are used to implement connections from cells configured to implement places to cells configured to implement transitions, and to implement connections from cells configured to implement transitions to cells configured to implement places. Edges can implement connections from cells configured to implement transitions to external components or other components within the neuromorphic device, which may, without limitation and by example, be a counter, a device to select one of a set of values, which may be digital, analog, or discrete, or a demodulator that produces a digital or analog signal that depends upon a signal received from a cell configured as a transition. Edges can also implement connections from external components or other components within the neuromorphic device to cells configured to implement places, where the external components or other components within the neuromorphic device may, without limitation and by example, be a counter, a device to accept an input of one of a set of values, which may be digital, analog, or discrete, or a modulator that converts a digital or analog signal to a signal that can be transmitted to a cell configured as a place. It is also possible to reverse the roles of places and transitions in the implementation of a Petri net, where places transmit signals to external devices as outputs from the neuromorphic device, and transitions receive signals from external devices as inputs using, by example and for illustration only, modulators, demodulators, counters, digital to analog or analog to digital converters, or other components as are known in the fields of electrical engineering and computer engineering. If the embodiment utilizes software or a combination of software and hardware to implement a Petri net, then the components that translate and transmit or receive signals to/from external devices of other components within the neuromorphic device may be implemented in software (NIDA) or a combination of software (NIDA) and hardware (DANNA.

The utilization of the neural hardware for the control of an external process or system 1080 is now described with reference to FIG. 10B. Note that control, or the influence of the behavior of the external process in a desired manner, is one of many possible applications, and that there are different types of control. An external process 1080 is shown that has at least one input and at least one output. These possibly multiple inputs and outputs are connected or interfaced to the neural hardware using, for example, a modulator and a demodulator 1070. For the purpose of this application, “modulator” is a term used to describe a device that converts values produced by the external process into one or more events, which may occur asynchronously or synchronously with a clock, where the events are applied to the neural network via the interface and control structure shown in the figure. As an example, the modulator may be a pulse-width modulator that converts a signal to a sequence of pulses of different width, and the leading and training edges of these pulses may be associated with events applied to the neural network. In a similar fashion and for the purpose of this application, a “demodulator” is a term used to describe a device that converts events produced by the neural network and delivered to the demodulator via the interface and control structure into a signal represented by values that can be applied as one or more inputs to the external process. As discussed elsewhere in this application, a modulator and a demodulator 1070 as described herein is only one way in which a sequence of events can be converted to a signal for input to an external process, and in which a signal output from an external process can be converted to a sequence of events. For example, a digital to analog converter (DAC) can be utilized to convert a signal's value at a given time to a digital representation, which may be a sequence of binary digits represented by high and low voltages, ones and zeros, or different currents, or the presence and absence of a voltage, current, or light, and this digital representation can be converted to a sequence of events by, for example, clocking the binary digits out of a storage device such as a shift register to be presented to the neural network as events.

There can be an arbitrary number of inputs and/or outputs, and that these outputs can be of different types. For example, they can correspond to signals that assume values in a continuous set between real numbers a and b, represented by the interval of values [a,b]. This value set can instead by a set of discrete values, which may be ordered, for example with values that can be placed in a one-to-one correspondence with the positive integers and that may represent a discretization of the interval [a,b]. A discrete value set can also be represented by a set of symbols, such as the letters of the alphabet, {a, b, c, . . . , z} or the union of this alphabet set with the numerals, {0, 1, 2, . . . , 9}, but other sets of symbols may be used. For example, the value may be an image, a portion of an image, or a pixel value from an image; (see, for example hand-written digit classification in NIDA U.S. patent application Ser. No. 14/513,280, of Birdwell and Schuman filed concurrently herewith).

Cells/elements of the neuromorphic device can be selected by the controlling and optionally optimizing device 1060 in FIG. 10B, via one or more of the interface and control structure and the configuration structure, and programmed to function as neurons, represented by the letter N in the figure, or as synapses, represented by the letter S. Furthermore, these programmed cells can be interconnected by action of the optimizing device to form a neural network. In FIG. 10B, the lines originating and/or terminating at a cell/element labeled N or S represent these connections, and the connections allow events to be transmitted from, for example, a neuron N 1012 through, for example, a synapse S 1014 to one or more neurons N 1016 and/or to/from synapses S 1018, 1020 respectively. In one preferred embodiment of the neruomorphic device, the cells/elements are organized as a two-dimensional array, and each cell/element may be connected to one or more of up to eight (or in an alternative embodiment 16, 24, 32 or other multiple of 8) of its neighboring cells. Furthermore, neurons N or synapses S may be connected via the interface and control structure 1040 as shown to send events to or receive events from a modulator, demodulator 1070, or other structure in order to influence or be influenced by an external process 1080.

FIG. 10B also illustrates a representation of a neural network that can be programmed by an optimizing device. An explanation of the operation of the neural network is provided. A signal is received by neuron 1012 from, for example, an external process 1080 after it has been converted to a sequence of events via its connection to Interface and Control 1040. This signal may, or may not, cause neuron 1012 to “fire”, where the firing process creates an event that is applied to the input of synapse 1014. A neuron N can be modeled as an accumulator that sums, or accumulates, weights associated by events applied to its inputs. The weights can be positive, zero, or negative; a weight of zero implies that events that arrive at the neuron's input on that signal line have no effect on the neuron. The value stored or computed by the accumulator is preferentially bounded between minimum and maximum values and is compared to a threshold value, and if the accumulator's value exceeds the threshold value, then the accumulator's value is reset to an initial value, which is typically zero, and the neuron 1012 creates an event that is applied to the input of synapse 1014.

Optionally, the neuron 1012 may have a non-zero refractory period parameter. If the refractory period is not zero and the neuron 1012 has fired more recently than this period of time into the past, the neuron 1012 will not fire again until the end of the refractory period. This functionality can be implemented with a count-down timer that is initialized to the refractory period when the neuron 1012 fires, and with logic that prevents the firing of the neuron 1012 if the count-down timer holds a non-zero value. Furthermore, the count-down timer stops counting down when it holds a zero value. Another way to implement the refractory period is with a RC (resistor-capacitor) network; where the capacitor is charged to an initial voltage when the neuron 1012 fires. The voltage across the capacitor can be compared to a threshold voltage, and circuitry can be utilized to prevent the neuron from firing if the voltage across the capacitor is greater than the threshold voltage. Note that in the preceding discussion the comparison could be “greater than or equal to” instead of “greater than”. Other implementations can be utilized, as are well-known in the art of electrical engineering and computer engineering.

If the weight associated with the signal line between interface and control 1040 and neuron 1012 is positive and events continue to arrive at neuron 1012's input along this signal line, neuron 1012 will eventually fire, causing an event to be presented at an input of synapse 1014. In a preferred embodiment, there is no weight associated with an input created by a neuron; instead, the weight is associated with a synapse and applied to events that traverse through the synapse and are applied to the input of a neuron. These weights may be associated with either the synapse or the receiving or destination neuron and its input signal line. The effect is the same in either case, but the manner in which the neuromorphic device is implemented may be different.

In a preferred embodiment, a synapse has an associated time delay, which may also be represented or viewed as a distance if an event propagation velocity is defined for the synapse. The time delay is applied to events that are applied to a synapse at one or more of its inputs, and the effect is that the events do not exit the synapse for application to a neuron's input (or an external process 1080 or other device) until an amount of time corresponding to the time delay has passed. Preferably a synapse may have more than one and possibly many events in transit via its implementation of a delay function, allowing the events to exit a synaptic output in the order they are received at the synaptic input and delayed by the time delay associated with the synapse. For example, if the time delay, which is a parameter of the synapse, is 5 seconds and the synapse receives an event A at time 2 seconds, the event produced at the synapse's output that corresponds to event A will not be emitted until time 7 (2 seconds plus a delay or 5 seconds). If a second event 13 is received at time 3 seconds, a second event will be produced at the synapse's output that corresponds to event B at time 8 seconds (3 seconds plus a delay of 5 seconds). When each emitted event is presented to a receiving neuron connected to or associated with one of the synapse's output, a weight value is associated with the emitted event, and the neuron uses that weight value to update its accumulator (unless the result would exceed an optional maximum or be less than an optional minimum accumulated value).

Thus, in a preferred embodiment, a cell/element can be programmed to represent either a neuron or a synapse, a neuron has an accumulator, optionally with a maximum and a minimum allowed stored value, a threshold, and an optional refractory period parameter, and a synapse has an associated time delay parameter and a weight, which may instead by associated with an input of a neuron. The configuration of a programmed neural network comprises the cells/elements of the neuromorphic device of FIG. 10B that are used to implement neurons and synapses, the connections between the neurons and synapses, and the parameters of these neurons and synapses. This configuration is preferentially initialized and possibly modified by the control and optionally optimizing device 1060 via the interface and control structure 1040 and/or the configuration structure 1050.

Neurons 1016 and 1022 and synapses 1018 and 1020 may comprise a loop in the depicted neural network. A loop may be regenerative in a neural network in the sense that, given appropriate initial conditions, one or more of its neurons may create a sequence of events indefinitely. Such a loop can be one example of a central pattern generator (CPG). The regenerative behavior is dependent upon the structure of the loop, the weights associated with the synapses or inputs to the neurons, and the time delays associated with the synapses. For example, if neuron 1016 has an initial accumulator value of 1 and a threshold of one, and if neuron 1022 has an initial accumulator value of 0 and a threshold of one, and if both synapses 1018 and 1020 have time delay parameters of 1 and weights of 1, then both neurons 1016 and 1022 will fire, creating an event, once every 2 seconds. If the time delay associated with either synapse 1018, 1020 is decreased (increased), then the firing rate of both neurons 1016, 1022 will increase (decrease). If the weight of synapse 1020 has a value of −1 instead of 1, then neurons 1016 and 1022 will each fire only one (unless possibly when a threshold is negative in which case it may be possible for a neuron to fire even upon receipt of an event having a negative weight); furthermore, a subsequent event input from synapse 1014 to neuron 1016 with a weight of 10 will cause neurons 1016 and 1022 to fire exactly once. Events produced by neuron 1022 can follow a path through the neural network comprising synapses 1024, 1026, and 1030, and neurons 1028 and 1032, to be received by interface and control 1040 from an output signal line represented by output 4 of neuron 1032, and such signal can cause a signal or change in a signal to external process 1080 via modulator and/or demodulator 1070. This, or a portion thereof containing one or more neurons and/or synapses, is an illustration of an implementation of a dynamic system using a neural network of the type described herein, where for the purposes of this application a dynamic system is a system, process, or device whose current output is determined by its current input and an internal state, and where such dynamic process may be coupled via one or more output(s) and/or input(s) to an external process 1080. In these cases, the internal state comprises the values of the accumulators in the neurons and any events that have been applied to inputs of synapses but for which corresponding outputs from the synapses have not yet been created or applied to inputs to neurons.

Now, methods for communicating with distant elements in a DANNA will be discussed. An array of circuit elements of FIG. 9A or FIG. 9B was first shown in FIG. 10A. In FIG. 10A, an element 1021 is shown with addressable Input/Outputs 0 through 8 in a simplified embodiment. Element 1021 may have, for example, eight inputs or outputs to other internal array inputs or outputs of other circuit elements. Similarly, element 1023, by way of example, may have Input/Outputs 0 through 8 which may connect to yet another circuit element internal to the array. Circuit elements 1031 and 1033 are shown as providing inputs or outputs to components external to the array devices (such as a display, a camera, a radio or scanner). A given element may exist in two or three dimensional space and so may be addressed with coordinates X, Y in space (Z if three dimensional space). Each I/O may be addressed as a number between 0 and 7 (FIG. 9A) or 0 and 15 (FIG. 9B). This address will be referred to herein as an I/O Address Select signal and proceeds from a control unit which may be a random number generator, a counter or other known means of generating addresses for sequential addressing of elements. The “I/O select address” of each I/O for connected elements may align so when each “element input” is sampled by that element, the element connected/driving this input is aware of the response to its “output”. There are many ways to “layout” and “connect” the elements. The two ways shown in the drawing FIGS. 11-19 are just examples. The key is the “I/O select addressing” and the ability of an element to determine how a connected element responds to its transmission of a “fire” condition.

An array of elements can be implemented using a FPGA or an ASIC device, as previously disclosed, using an element that is configurable and programmable and that can communicate with its eight (8) nearest neighbors using communication links for input and output, as shown in FIG. 10B showing an exemplary array of elements of a DANNA with a communication path shown. Note that the array can be of any size by repeating the pattern of any 2×2 block of elements along an edge (or a portion thereof). The inputs and outputs in this figure are numbered in order to identify the inputs and outputs in adjacent elements to which they are connected. To elaborate, consider FIG. 12A, which is a subset of the above array, namely a 3×3 array of elements (neurons or synapses). The center element 1210 in this 3×3 array may communicate with its eight neighbors using the middle communication link along each side to communicate with the element immediately to the left, right, top, or bottom, and may use the corner communication link to communicate diagonally with one of the four corner neighbors using a two-dimensional I/O address select signal. The numbering system is arbitrary but in FIG. 12A, for example, I/O 6 of 1210 may communicate with I/O 6 of 1205 while I/O 2 may communicate with I/O 2 of element 1215. As discussed above, elements 1205, 1210 and 1215 may selectively be a neuron or a synapse.

This same connectivity pattern can be utilized to connect any element with up to eight (8) additional elements located more distantly from the element. The approach can be applied more than once to provide connectivity to elements at different distances from any element, and any element may be so connected. The central element 1210 must acquire inputs from each of the adjacent elements for which the input line from that element is enabled. (Enabling and disabling is determined by a set of binary values in the central element 1210, each value corresponding to one of the inputs.) In a hardware implementation, it is advantageous to sample the enabled inputs sequentially (although not necessarily in the order shown in the diagram) because this requires significantly less complexity (and area) in the implementation of the element. Sequential sampling implies there is an order in which the enabled inputs are read, and when long-term potentiation (LTP) or long-term depression (LTD) is implemented to affect the future values transmitted from the adjacent elements to the central element, the order of sampling can significant.

In a preferred implementation, inputs from adjacent enabled elements are sampled sequentially. Consider the clock signals shown in FIG. 10C. The Global Network Clock, otherwise known as the firing clock, is labeled G_N_C. The Acquire Fire Clock, labeled A_F_C, is used to sequentially select each input (using the 3-bit Global Input Select signal, labeled G_I_S, assuming there are eight inputs as in the diagram above) and operates at a frequency eight times the frequency of the G_N_C. These clocks are also shown in FIGS. 9A and 9B for each of an 8 I/O embodiment of an element and a 16 I/O embodiment of an element respectively (but labeled differently).

Long term potentiation (LTP) and long term depression (LTD) functions are implemented by synapses and modify synapse weights. A design alternative is to implement LTP and LTD in the inputs of the neurons. The current value of a synaptic weight is gated to the output of the synapse at the beginning of a G_N_C cycle (preferably but not necessarily the leading edge) if the output of the synapse's FIFO indicates that an output should be generated; otherwise a weight of zero is gated to the output. LTP and LTD are implemented by monitoring the output of an adjacent neuron, which is specified by the configuration of the synapse. The neuron's input from the synapse should be enabled; otherwise, no LTP/LTD occurs within the synapse.

Referring again to FIG. 12A, suppose that central element 1210 of the above array is configured as a neuron and the two horizontally adjacent elements 1205 and 1215 are configured as synapses. LTP/LTD should occur symmetrically on all synapses connected to enabled inputs of a neuron. To accomplish this either the order in which the neuron's inputs are sampled should be randomized, or the initial input to be sampled should be randomly selected, after which the inputs are sampled sequentially. The second approach is preferred. In this case, the neuron 1210 of FIG. 12 may sample, in successive G_N_C cycles, inputs in the order (3,4,5,6,7,0,1,2), (1,2,3,4,5,6,7,0), (4,5,6,7,0,1,2,3), . . . , where the first input sampled (3, 1, 4, . . . ) is chosen randomly with approximately equal probability. The parentheses are merely used to group input indices into groups of 8 corresponding to cycles of the G_N_C and the assumed eight inputs of each element. It is preferable that all elements of a neuromorphic array utilize the same input sampling sequence. This reduces the complexity of the implementation, and it also significantly simplifies the logic necessary to implement LTP/LTD in the elements configured as synapses 1205 and 1215. This is because when a neuron's input, such as 1210 is connected to a synapse's output, such as 1205 the synapse knows when its output is sampled by the neuron and thus when it needs to monitor the neuron's output to detect if the output generated by the synapse caused the neuron to fire. Furthermore, the synapse can monitor the neuron's output before the neuron samples the synapse's output and determine if the neuron has already fired during the current cycle (caused by a different input or an input sampled during the previous cycle of the G_N_C) and is therefore in its refractory state. If instead the order in which the neuron's inputs are sampled is randomized, each input should have approximately equal probability of selection for sampling. In this case one method to implement LTP/LTD requires an additional signal line from the neuron to the synapse to provide an indication that the neuron fired because of that synapse's input.

A number of different methods and implementations exist in the digital hardware literature to enable the random selection of an input to a neuron. As suggested above, a random number generator may be used. Or, for example, a linear feedback shift register can be used. A second method and implementation is to store a large number of randomly generated values to be used to select the first input to be sampled during each G_N_C cycle. A third method is to store digits of an irrational number, or a long sequence of non-repeating digits. A fourth method is to sample an analog noise source such as a reverse biased diode junction or a source of thermal noise in order to choose one or more binary digits. A fifth method is to use a digital signal processor (DSP) block to compute a sequence of pseudo-random digits or binary values using, for example, a cryptographically sound random number generator algorithm or a software implementation of a linear feedback shift register or a linear congruential generator. Several of these methods can be implemented in hardware without resort to an algorithm implemented in software and executed by a DSP or other processor.

The numbering scheme (0, 1, 2, 3, 4, 5, 6, 7 or 0-15 or 0-24 (a three ring element has been constructed with a ring structure analogous to that shown in FIG. 15) is arbitrary as is the sequence through which the hardware (DANNA or control unit) implements the scans of the elements. Greek letters or pictographs could be used instead of numbers. Whatever the symbols used and whatever sequence is used to interrogate inputs and to produce outputs by elements, two elements that are connected by an input/output line(s) must synchronize their actions with respect to that line in order to implement LTP/LTD (and, each element must do this with every other element to which it is directly connected by an input/output line(s). The numbering schemes given are one example; other obvious examples would be to reverse the numbering or order in any or all rings or circles or layers of numbered I/O lines, and to interleave the numbering or ordering of I/O lines between such circles, rings, layers. Any numbering scheme or permutation of these numbers will work, as long as all numbers or symbols are replaced by permuted values.

The pattern of interconnections between elements can be repeated by connecting from each element to 8 (16, 24) elements not adjacent to said element, as for example disclosed in some of the figures, and the same (or a similar) pattern of interconnections can be used multiple times to provide connections among all elements. The figures described further herein such as FIG. 15 disclose ways to do this using, for example, 4 equivalent patterns of interconnections for a distance 2 layer (FIG. 16), 9 for a distance 3 layer (FIG. 17)), and 25 for a distance 5 layer (FIGS. 18 and 19). By example, and referring to FIG. 15, element 1520 is connected to adjacent elements 1504 a/1504 b, 1512, 1525, 1526, 1505 a/1505 b, 1510, 1518, and 1508 using a distance 1 layer or ring structure and input/output signal lines labeled with the digits 0, 1, 2, 3, 4, 5, 6, and 7 (where 1504 a/1504 b and 1505 a/1505 b had two rings or layers). In this example, all of the elements (1502 a/1502 b, 1508, 1504 a/1504 b, 1512, 1506, 1516, 1518, 1520, 1525, 1528, 1515 a/1515 b, 1510, 1505 a/1505 b, 1526, 1530, 1514, 1522, 1524, 1532, 1534, 1535 a/1536, 1536, 1540 a/1540 b, 1542, and 1545 a/1545 b) are connected to their adjacent neighboring elements in this manner. Note that the “a” and “b” designations in the elements' reference numbers in FIG. 15 refer to the distance 1 layer and distance 2 layer input/output signal lines, respectively. In a like manner, elements 1502 a/1502 b, 1504 a/1504 b, 1506, 1515 a/1515 b, 1505 a/1505 b, 1530, 1535 a/1535 b, 1540 a/1540 b, and 1545 a/1545 b are connected to elements at a distance of two (skipping one intervening element) using, for example, the same pattern of interconnections used for the distance 1 layer connections. By example, element 1505 a/1505 b is connected to elements 1504 a/1504 b, 1506, 1530, 1545 a/1545 b, 1540 a/1540 b, 1535 a/1535 b, 1515 a/1515 b, and 1502 a/ 1502 b using a distance 2 layer or ring structure and input/output signal lines labeled with the digits 8, 9, 10, 11, 12, 13, 14, and 15. The input/output signal lines so numbered are indicated by the reference numbers containing the “a” designation in the instances where, for clarity, this distinction has been made, as in the portion of element 1505 a/1505 b referenced by 1505 a. In order to implement distance 2 layer connections for all elements, four (4) patterns of interconnections are necessary, corresponding to the pattern of heavier lines in FIG. 15 and three similar interconnection patterns (not shown) including one of elements 1508, 1516, and 1518. This is illustrated in FIG. 16 by representing each element as a circle shaded with one of four patterns corresponding to one of the four patterns of interconnections among elements having like shading. Not all interconnection patterns of a distance K layer (K an integer and at least one) need be implemented; for example, 0, 1, 2, 3, or 4 may be implemented for a distance 1 layer of interconnections, and any N may be implemented, where N is an integer between 0 and 25, inclusive, may be implemented for a distance 5 layer of interconnections. Examples that indicate the possibility of one or more layers corresponding to distances 1, 2, 3, and 5 are illustrated in FIGS. 15-19, where the areas enclosed by the dashed lines indicate the number of possible interconnection patterns for layers of different distances.

Another aspect is the randomization of the choice of the first I/O line to be used by an element during each cycle, after which the other elements are used in a predefined sequence. The utility of this randomization is to ensure that on average all elements' outputs are treated equally by a receiving element so that LTP/LTD effects are equally probable in each of the connected elements. This prevents one element from “hogging” the effects (for example, claiming credit for making a neuron fire) of all LTP/LTD activities with a connected element.

Yet another aspect is the manner in which LTP/LTD is implemented. As an overview, an element (configured as a synapse) that delivers an event to a receiving element configured as a neuron watches the receiving neuron's output line (that returns to the synapse) to detect whether the neuron is already firing (in which case there is a LTD effect) or fires in response to the delivered event (causing LIP). This “watching” occurs at a specified point in time after the delivery of the event to the neuron, and the hardware is designed in a manner that allows the synapse to determine whether its event, or an event delivered by another synapse, caused the neuron to fire.

Referring again to FIG. 12A, suppose that element 1205 is configured as a synapse, and that the element is configured as a neuron 1210. Assume that input 6 of the neuron 1210 is enabled and that the synapse 1205 is configured to monitor its input/output signal line 6 to detect when the neuron 1210 fires. When the synapse 1205 emits an event (a weight) on its outputs, the neuron 1210 detects that event. The neuron 1210 adds the weight received on input 6 to its charge accumulator, and then either (a) the neuron's charge state is not sufficient to cause the neuron to fire, in which case either the next input is sampled or the neuron 1210 presents its output to its neighbors (after all inputs have been sampled) or (b) the neuron 1210 is not refractory (has not determined previously during the current firing cycle that it must fire and is not already firing) and its charge state is sufficient to cause the neuron to fire, in which case it changes its output to indicate that it is firing on the next phase of the firing clock, or (c) the neuron 1210 is refractory (has determined previously during the current firing cycle that it must fire or is already firing), in which case it samples the next input or presents its output to its neighbors.

It is preferred that the neuron 1210 indicate on its outputs that it will fire on the next G_N_C cycle immediately or soon after its determination that it will fire. Note that in this preferred design only the neuron's output at the beginning of each G_N_C is sampled to connected elements to determine if it has fired. By changing its output mid-cycle, connected synapses are able to determine when their outputs caused the firing event, or that their output could not cause the neuron to fire because it is in its refractory state and is already firing.

The Dynamic Artificial Neural Network Array (DANNA) hardware definition may specify a grid of elements, each of which that can be defined as either neurons or synapses. Each element can connect to eight (16 or 24 and so on) of its neighbors. Depending on the type of element, this connectivity may be restricted. For example, one definition of a synapse only has one enabled connection from another element and only connects to one element (which may be the same element). Thus, the other six or seven output ports are not in use. Because of this definition of a synapse, arbitrarily defining a path in the grid may inadvertently cut off a portion of the grid from the current network. Other definitions of a synapse are possible, allowing multiple inputs. If multiple outputs are allowed, one can be monitored by the other synapse to implement LTP/LTD without introducing logical ambiguity.

Moreover, there are many structures that do not utilize as much of the connectivity of the network as may be needed to solve many complex problems. Thus, it may be advantageous to pre-define a grid structure, so that when designing the network, only parameters are optimized (thresholds of the neurons and delays and weights of the synapses). We define one grid structure in terms of a 4×4 element block and discuss possible permutations of that grid structure. An example of a 4×4 element block that we define is given in FIG. 12B.

Each arrow represents a synapse in FIG. 12B. In all 4×4 blocks, neurons are placed at coordinates (r, c) where r and c are both even (assuming both row and columns are indexed starting at zero). Synapses on even rows are one of the following (where all synapses in that row are of the same type): ← and →. Synapses in even columns are one of the following (where all synapses in that column are of the same type): ⇑ and ⇓. Synapses in odd rows and odd columns are one of the following: ⇑, ⇓, ←, or →. For this definition, interior neurons (those that are not along a border) are guaranteed to utilize at least four of their connection ports: the port to the element directly above, the port to the element directly below, the port to the element directly to the left and the port to the element directly to the right. Moreover, two of these are incoming connections, and two are outgoing connections.

These 4×4 blocks of elements (FIG. 12B) may be tiled together to form arbitrarily large networks. These larger network blocks have built in cycles (FIG. 12C) that are likely to be useful in many computational tasks, as we know that “cyclical” connections play important roles in the mammalian brain. FIG. 12C shows (4) 4×4 element blocks (forming a square) and also shows a first highlighted path 1222 forming a counterclockwise loop and a second highlighted clockwise path 1224 which loops may overlap one another. Loops 1222 and 1224 are examples of cycles in this tiled 4×4 example.

Consider by example the following design: Assume that the neuron samples each of its enabled inputs (assume there are eight) at the beginning of one clock cycle of the A_F_C, a clock operating at 8× the frequency of the G_N_C. Assume also that the neuron and synapse have agreed upon an input/output signal line numbering scheme such as is shown in the first diagram under “Random selection of inputs”. In particular, such a numbering scheme requires that adjacent elements use the same index number to refer to the input/output signal line that connects them, as shown. Assume also that the adjacent elements use the same sequence of indices to sample input signal lines during each G_N_C cycle; for example, they might use the sequence (3,4,5,6,7,0,1,2) or the sequence (3,5,7,1,2,4,6,0). Regardless of the sequence, because of this agreement the neuron samples its input signal line 6 during the same A_F_C cycle as the synapse that generated that input determines whether its output caused the neuron to fire, or whether the neuron is in its refractory state.

LTD/LTP Definition and Operation:

When an element is programmed and/or is operated as a synapse, it has the ability to potentiate (increase) or depress (decrease) its weight as a function of the impact its “output firing” has on the neuron connected to its output. This potentiation of a synapse weight is referred to as “Long Term Potentiation” or LTP. We refer to the depression of a synapse weight as “Long Term Depression” or LTD. If a synapse's firing causes its connected neuron to fire, it will potentiate its weight by a predetermined amount (in one example implementation, it increments its weight by 1). If a synapse's firing occurs while its connected neuron is already in a “firing state”, it depresses its weight by a predetermined amount (in our example implementation it decreases its weight by 1). The amount of potentiation and depression is the same for all synapses in an array and can be set during the arrays' implementation.

Each synapse of a DANNA may monitor the firing state of the neuron connected to its output so it can determine if its weight is be altered. To support this function, the I/O of each element may be assigned an “I/O select address”. There may be, for example, 16 I/O select addresses for arrays using elements with 16 I/O ports (FIG. 9B, for example). Elements may be connected in the array such that the I/O ports used to connect elements together have the same I/O select address. Since each element has access to the output port of each of its connected elements, this I/O select address assignment allows an element to monitor the firing of each element connected to its I/O. A global I/O address generator may be used to sequence the sampling of each I/O for the elements in an array during a single array cycle. This address sequencing and the assignment of the same I/O address to the connections between elements allows each element to monitor elements assigned to it as an output element.

We define an “output select register” as a programmable register in each element that indicates which I/O port (or address) is being used as the active I/O port (input enabled) by a connected element. The “output select register” is only valid when the element is programmed as a synapse. A synapse may be defined as having only one of its connected elements enabled to receive its output. When the I/O select address matches the contents of the output select register and a synapse is in a firing state, that synapse can sample the firing state of the element programmed as its connected output neuron.

There are three possible conditions which can result from a synapse firing: 1. The output neuron does not fire; 2. The output neuron fires at a time associated with sampling the input associated with the connected synapse; and 3. The output neuron was already firing, caused by another firing connected synapse who's I/O was sampled earlier in the network cycle.

A network cycle may be divided into 16 clock cycles (for arrays with elements with 16 I/O ports such as FIG. 9B). If a neuron fires one clock cycle after a particular I/O select address (the point at which the neuron samples this I/O port), the synapse associated with this I/O port will assume another synapse caused the neuron to fire and depress its weight if it is presently firing (condition #3 above). If a neuron fires two clock cycles after an I/O select address, the synapse associated with this I/O port will assume it caused the neuron to fire and potentiate its weight if it is presently firing (condition #2 above). If a synapse detects no firing by its connected neuron, its weight sees no change (condition #1 above). Note that the choice of “number of cycles” after an I/O address select to sample a neuron's firing state may be driven by the state machine design (LTD/LTP State Machine in either FIG. 9A or 9B) of the element and somewhat arbitrary. We could have shortened or lengthened this sample point by one clock cycle as well.

An optimization procedure can be used to evolve a DANNA network by modifying the structure of the network, as determined by the number of elements used, the type of each element, and their adjacencies relative to each other, and/or the configuration parameters of one or more network elements. It can also be advantageous to modify the network clock frequency (G.N.C.) using the optimization procedure and a programmable clock. This allows the speed of operation of the network to be tuned to the time constants or other dynamic characteristics of a process (hardware, software, or mixed) to which the network is connected, providing improved performance or improved adaptability or tuning to current process conditions. Selection of DANNA components and structures may be made to improve overall speed of operation and reduced power consumption with a particular external process or environment and so tuned to the environment by careful selection of analog and digital components of circuit elements of a DANNA.

A method for on-line learning using two populations of DANNA networks (or combination of NIDA/DANNA networks) is described. In this method, a period of off-line learning may be required. A population of networks that will be trained to accomplish a task is maintained and a learned model of the environment is also maintained. The learned model can also be a network as described herein, another neural network type, or any other model of the environment that can be adapted over time as the environment changes. During the period of off-line learning, the model of the environment is learned, and the networks of the population are trained based on the success of their interactions with the model of the environment, the environment itself, or a combination of the two. Alternatively, a physically based model, or a model determined using the principles of mathematics or physics, of the environment can be defined, and the networks of the population are trained based on the success of their interactions with this model of the environment, the environment itself, or a combination of the two. In some applications it may not be possible to use a period of off-line learning to determine a population of networks. In this case other methods may be used. For example, the networks may be specified manually or designed based upon the mathematics or physics of the model of the environment.

At the end of this off-line learning period, or when the population of networks has been defined, this population of networks remains in software as a simulation or as a hardware implementation in one or more FPGA, but one or more of the best networks in the population are chosen to become “production” level networks that are preferably implemented in hardware. A combination of one or more of the output(s) of these production level networks is used to interact with the environment, and again, the networks are judged based on the success of their interactions with the environment (potentially also with the model of the environment). All of the networks may be so judged, or a subset of the networks may be judged. Such a subset may be randomly chosen or chosen according to an algorithm that during multiple cycles chooses all of the networks at least once.

Preferably the model of the environment in software is updated as the environment changes. The networks that are simulated in software remain at the “development” level and interact only with the current model of the environment. If or when a network in the “development” level outperforms one of the networks in the production “level” using the current model of the environment, the network at the development level is implemented in hardware using, for example, the disclosed array of neuromorphic elements, where the array may be located in a hardware component that is currently used by the production networks or a different hardware component, and interactions with the old production level network are shifted to the new network, while the old production level network is offloaded or read from the neuromorphic hardware (DANNA), and either added to the development population of networks implemented in software (NIDA) or removed.

The production and development populations of networks can be implemented in hardware and software, respectively, as disclosed above, both in hardware, both in software, or in software and hardware. The hardware may consist of one or more components, which may be neuromorphic and may be implemented according to the designs disclosed herein. The production hardware and development software implementation and the implementation where both production and development networks are implemented in hardware, are preferred.

FPGAs such as those fabricated and offered for sale by Xilinx and Altera may contain digital signal processor (DSP) blocks implemented within the FPGA. Such DSP blocks can be programmed and can execute a software program to process input signals and produce output signals. The FPGA can be configured so that some input signals to a DSP may originate with one or more neuromorphic DANNA elements as described herein. For example, the input signal to a DSP block may be the accumulated charge in a neuron, LTP/LTD events that occur in a synapse, the output from or input to a synaptic FIFO or a synapse, the number of inputs to an element that simultaneously receive an event or non-zero weight, the firing events of a neuron, or the input indices in a neuron that cause the neuron to fire or that have input events that are received while the neuron is in a refractory state. The input signal to a DSP block may also be a signal generated or sampled externally from the FGPA and received by the FGPA or an error signal that indicates the deviation of an externally measured value from a desired or expected value, or from a value predicted by a model, where the model may be implemented and simulated by a processor, the DSP block, or another DSP block. This list of kinds of input signals is not intended to be exhaustive. In each case, the input signals are a function of time and may be sampled on a recurring basis and represented as a sequence of sampled values or may be a sequence of events. In the latter case an event may be a time of the event's occurrence or may be a time of occurrence and a value.

The software in the DSP block can implement a quality function to compute a metric indicating the quality or performance of an artificial neural network (ANN) or a portion of a ANN, or of a selected set of ANNs. The output of such a DSP can be used to guide an evolutionary or other optimization strategy to attempt to improve the performance of one or more ANNs as it interacts with a process or system, such as a physical system that exists externally to the FPGA. The software in the DSP may also implement a function that produces a sequence of values that are communicated to a device external to the FGPA such as a computer or another FPGA or a communication link.

It is possible to create DANNAs using one or more synapse and one or more neuron that use at least one output of an element of the DANNA to regenerate the behavior of the DANNA, causing an output of the DANNA to behave cyclically. A simple example is an adjacent neuron/synapse pair where the synapse is configured to implement a signal delay line of k>0 G_N_C cycles. If the synapse is configured to always emit the maximum weight value (or another weight value) that is guaranteed to cause the neuron to fire when that event is received by its enabled input, then once the neuron fires, it will continue to fire at least once every k>0 G_N_C cycles. This structure is an oscillator and is a simple example of what are termed central pattern generators in neuroscience.

Given a periodic input event sequence to a DANNA and a desired periodic output event sequence, evolutionary optimization can be used to determine a DANNA—an interconnected collection of neuromorphic elements or simulated neurons and synapses—that accepts that input sequence and generates the desired periodic output event sequence. By using a DANNA to create a cyclic input event sequence, as in the paragraph above using one neuron and one synapse, it is also possible to create a DANNA that will generate any desired arbitrary periodic output event sequence, and sets of such periodic output event sequences with specified relationships among them without any external input. This can be done using either hardware components such as those described and implemented using one or more FPGAs, or using a software (simulated) DANNA/NIDA or NIDA. This can be used, for example, to implement a pacemaker, a neural simulator that may be implanted, an oscillator or component of a mixer, modulator or demodulator for a radio or the communication system, and a joint controller or actuator mechanism for a robotic device.

A third modality is the creation of a DANNA that generates a desired finite event sequence in response to an input event. This is also possible using evolutionary optimization and either a hardware or software implementation of the DANNA/NIDA. The DANNAs that are created in this manner may incorporate examples of central pattern generators (CPGs). A CPG can be used to control the motion of a device such as a robot's arm or leg, to communicate a signal in response to detection of an event or condition, which may be done using an ANN such as has been described in the BICA 2013 paper by C. Schuman and J. D. Birdwell, or by using classifiers and/or detectors as are known in the arts of electrical and computer engineering and computer science. For example, a DANNA CPG can be used to control the motions of the legs of small autonomous vehicles or robots. An advantage of a CPG designed and implemented using these technologies is that it can appropriately respond to other signals (inputs) from its environment.

Over the course of evolutionary optimization, parameters and placement of neurons and synapses are manipulated to produce networks to solve tasks. Rather than limiting the optimization to single element changes, a sub-network of two or more elements that is known to be useful (e.g. a central pattern generator) can be added to the current DANNA network. A “toolbox” of simple components that are known to be useful can be used as both building blocks and additions to DANNA networks. The newly constructed network does not have to relearn how to build the simple components; it can take advantage of those simple components that are pre-built, thus learning or training time can be reduced.

Another use of sub-networks in a DANNA is the formation of collections of identical or highly similar sub-networks in a larger network. For example, a sub-network in a library or sub-network may have utility in the detection of a feature in an image, where the feature, by way of example, can be a horizontal, vertical, or slanted line. An array of sub-networks can be defined in a larger network by locating the origins of the sub-networks onto a two-dimensional grid of coordinates within a rectangular region used to represent, input, or output an image, which may be one frame of a video or movie. In this manner an ANN can be formed that processes all or a selected subset of the pixels in an image in parallel to find, by way of example, the horizontal lines in the image and produce an output image whose pixel values represent the presence of these lines at various locations within the input image. Different sub-networks can be utilized to detect or classify other types of imagery such as, for example, edges of images of objects, in-focus portions of an image, and portions of a selected color, level of saturation, or lightness.

Simple networks may be hand-tooled to perform certain tasks and then replicated across a larger network to perform more complex tasks. For example, a small network or substructure to detect a line in a small image may be replicated to build a larger network to recognize lines in larger images. It may also be useful to design an existing structure for one problem and tweak that structure or weights in that structure for a similar, though slightly different problem. For example, one task might be recognizing piano notes. The structure to recognize one note (e.g. F) may be very similar to the structure required to recognize another note (e.g. F#), but the distances or delays may need to be scaled. This general idea has wider applications as well, such as frequency recognition, edge detection, and character recognition.

One may also develop a library of components or NIDA/DANNA (one or the other or both to construct more complex or simpler network architectures or sub-networks) that are analogous to components needed in signal processing, communication systems or controls. Examples include oscillators, band pass and band stop filters, feedback regulators, and pattern generators. Such a library can be utilized to select possibly useful sub-networks as discusses above using evolutionary optimization. One could use the library to handcraft solutions to particular applications.

In order to better teach this method and DANNA apparatus, consider a redrawn representation of an array of elements with space inserted between the elements for clarity, as shown in FIG. 13 which shows an array of elements with space added between elements for clarity. The connections between elements may now be explicitly represented by lines as shown in FIG. 14, an array of elements with connections illustrated as lines (wherein the diagonal lines do not connect at the center of their X shapes).

Now, one may create a second set of eight connections between selected elements by skipping every other element, as shown in FIG. 15, an array with a second set of connections, skipping every other element (and so forming a three dimensional embodiment). In FIG. 15, the original connections have been rendered in light gray in order to emphasize the new connections. For clarity we refer to the two sets of connections as the first (original connections to nearest neighbor) and second rings or layers of connections, and we have labeled the second rings of connections using the numbers 8-15. Note that other labels can be used for any ring or layer.

The elements that do not have the second ring of connections in FIG. 15 can be connected using their own second rings in their own network of connections. When every other block is skipped, we call this a level-2 ring, and a total of four networks of level-2 ring connections are necessary in order to provide level-2 connections to all elements, although there is no requirement that all elements must have level-2 rings. To illustrate this possibility we simplify the visual representation of the elements by representing each element as a circle and omitting the connecting lines in FIG. 16 (showing four sets of layer-2 interconnection networks illustrated by four different types of shaded circles representing the elements that participate in each level-2 network). Note, however, that the connections are still present, as are the connection labels (whether numbers or otherwise); we have just suppressed their visual representation to offer a less cluttered drawing. Four different types of shading are utilized in this figure to indicate which elements are members of each level-2 network of connections.

Referring to FIG. 15, we define a face of a DANNA as an edge, a plane or a collection of signals along one or more edges of a DANNA in a hardware implementation that exists in three dimensional space. A face may be grouped with a subset or all of the input signals, a subset or all of the output signals, or a mixture. For example, one face of a cube will be associated with all inputs and outputs, where the network extends back into the cube, and a hierarchical description of the network allows the formation of hardware or simulation analogs to the cortical columns that are known to exist in the neocortex. As another example, a DANNA (or NIDA) can be constrained to be in a hexagon. In this case, one or more faces of the hexagon would be associated with a subset of the DANNA's inputs and/or outputs, and multiple hexagons could form a tiling of a two-dimensional region having identical or similar DANNAs within each hexagon that connect along the faces (edges) of each hexagon. Any other polygon or set of polygons can be used that can be arranged to create a tiling of a two-dimensional region, with DANNAs similarly associated with each polygon and the DANNAs interconnected across the faces or edges. The same tiling procedure can be utilized with networks defined within and associated with a bounded three-dimensional polyhedron, and multiple polyhedra can be used to tile a region of three-dimensional space. Multiple polyhedral shapes can be used to create the tiling. Other inputs or outputs are explicitly allowed since only a subset of the inputs and/or outputs of each DANNA associated with a polygon or polyhedron need connect to other DANNAs across a face or edge. In this manner the tiling of DANNAs can be used to implement, for example, a DANNA (consisting of a collection of DANNAs (or NIDA's) associated with the tiled polyhedra or polygons) that exhibits grid cell behaviors, as are observed and may be known in the neuroscience literature that can track external features using signals measuring characteristics of those features. For example, such a DANNA could exhibit grid cell behavior that tracks an object observed using a visual (visible light, infrared, or ultraviolet, but also including radar or sonar systems and laser scanning systems) by firing a geometric pattern of neurons within the DANNA in response to the acquired signal.

There are known methods for stacking integrated circuits to form, for example, stacked DANNA's. It is desirable to keep signal lines short and stacked arrays compact to promote speed of operation. Use of analog components selected for their ability to conserve power in circuit elements of DANNAs may promote overall power savings. In a novel embodiment, we disclose the use of “channels” (etched out) in the surface of the silicon (Si) to form “tunnels” when multiple Si chips are stacked and interconnected (bonding being resolved in various ways known in the art). The tunnels are created to form regions for air or fluid flow for cooling the integrated circuits, the concept being to pressurize one side of the air/fluid and push it through the channels (for example, inert gases such as Ar or He could be used). These tunnels may be etched in a second dimension (e.g., “holes” through the Si wafer created during fabrication). Problems with stacking chips are removal of heat and bonding between layers, but these are solved with known bonding methods and the cooling methods as suggested above depending on the integrated circuits to be stacked. While multiple layer devices have been fabricated, thermal management problems can be significant depending on the amount of heat generated and the ability to use cooling fluid (including gas) to alleviate the generated heat, limiting the depth of the “stack”. This concept is similar to air conditioning (or water cooling) for stacked Si devices. One Can do stacking without the cooling channels/tunnels, up to a point, dependent on the generated heat.

The concept of inclusion of sub-networks, either as building blocks of the greater network or as additions to existing networks may be applied to DANNA's. Such sub-networks can be parameterized, and the parameters can be selected or tuned using the methods of evolutionary optimization or other optimization methods such as gradient search and Newton's method. For example, a parameter of a sub-network can be the placement of a designated coordinate, the origin of the sub-network, in the sub-network at a specified location within another network or sub-network. Such a coordinate can be a location in a two-dimensional or three-dimensional region of space or one or more indices into a DANNA, such as a hardware array of neuromorphic elements that may, for example, be implemented using a FPGA. Additional parameters can be selected or tuned to scale the size of the network in one, two, or three dimensions, or the delays in the network, for example by scaling the size of the FIFO queues in synaptic elements of the disclosed neuromorphic array. A clock rate or clock divider, or other parameter may be used to tune a frequency of an oscillator of a CPG, a resonant frequency, or upper and/or lower cut-off frequencies of sub-networks design as filters or detectors. In other words, in addition to adapting parameters of single elements in the network or of the network as a whole, we may also adapt parameters of entire sub-networks within the greater network. Sub-networks of one or more DANNAs can have sub-networks, resulting in sub-sub-networks of a higher-level network. In this manner, a hierarchical description of a network's structure can be maintained. Evolutionary optimization can be performed at any level of this hierarchy and may be performed recursively to obtain one or more networks that achieve a specified objective.

Other levels of connectivity can be defined and implemented, as shown in FIG. 17. FIG. 17 shows a level-3 network of connections between selected elements, indicated by bold circles around those elements. If level-3 connectivity is desired for every element, then nine (9) such level-3 networks are needed, each having connections to exactly one of the elements within the square indicted by dashed lines. In FIG. 17, a level-3 network of connections is illustrated between selected elements (indicated by bold circles around these elements). The possibility of four (4) level-2 networks of connections is illustrated by the four types of shadings of the elements; however, this is optional. The DANNA may have only level-1 (nearest neighbor) and level-3 connection networks. If level-3 connections are desired for all elements of the DANNA then nine (9) level-3 connection networks are necessary, where each of these nine networks will have connections to exactly one element within the square illustrated by the dashed lines. Now element monitoring will be described with reference to an interconnected DANNA having a plurality of interconnections, all of which elements of the array may be monitored.

Element Monitoring:

A challenge with implementing a large array of neural network elements in an FPGA is the ability to read the state of each element in the array. Referring now to FIG. 15B, the use of a shared bus structure may not be possible in an FPGA given the lack of shared bus drivers for internal logic (open-source or tri-state). As the number of circuit elements of an array such as a DANNA grows, the loading on a shared interface can also become high for optimal operation. An approach defined below provides the ability to read the state of each circuit element (selectively operating as one of a neuron and a synapse) in a dynamic adaptive neural network architecture (DANNA) in real-time while the neural network of neurons and synapses is in operation.

Referring to FIG. 20, there is shown a DANNA of X columns and Y rows having an output register 2005 for selectively receiving outputs from read registers of circuit elements which may be monitored as follows. The following functions are needed to support reading of each circuit element in a DANNA implementation: 1. A global “load read register” command signal 2001 for circuit elements at columns 0-X and rows 0-Y generated by the interface logic to the array; 2. A global “shift read register” command signal 2002 for circuit elements at columns 0-X and rows 0-Y generated by the interface logic to the array; 3. A “fire counter” 2003 in each element of the array, for example, a 16 bit counter, which tracks the number of fire states the element has experienced since the last “load read register” command; 4. A “read register” 2004 in each element of the array which captures the active neuron-charge or synapse-weight value and “fire counter” value for the element upon an active “load read register” command. Note the “read register” 2004 may preferably be a parallel-load register (for example, 16 bits received at Data In) with serial-output/serial-input data-transfer capability shown as Serial In and Serial Out respectively; 5. A connection matrix which connects the serial output of a “read register” of an element in a column of the array to the adjacent element's “read register” serial input (see, for example, Serial Out connection from Element (0, 0) to Serial In of Element (0, 1) or Serial Out connection from Element (X, 0) to Serial In of Element (X, 1); and 6. An “output register” 2005 which sets at the top of the element array and captures the serial-output (Serial Out) of the “read register” 2004, for example, of the element at the row Y end of each chain of elements in a column 0 to X. The “output register” 2005 may provide data for the X columns to an external interface of the DANNA array component.

Each circuit element may capture in its “fire counter” 2003 the number of fire events it has experienced between “load read register” 2001 commands. Upon the array receiving a “load read register” command 2001, each circuit element of the DANNA loads its read register 2004 with the contents of its “fire counter” 2003 and the active charge value (loaded at Data In from Accum Register 2006 if the element is programmed as a neuron, or the active weight value if the circuit element is programmed as a synapse. The circuit element also resets its “fire counter” 2003 after each “load read register” command. The “read register” 2004 is, for example, a parallel-load shift register connected in a serial chain across each column in the array of elements (shown by dashed lines labeled “load”). On each “shift read register” command 2002 the contents of the “read registers” 2004 in the array are shifted one position up the column of “read registers” 2004 with the “read register” 2004 at the top of each column 0 to X shifting its content into the “output register” 2005. Upon each “shift read register” command 2002, the values shifted from the “read register” 2004 into the “output register” 2005 is provided to the external interface of the array as Output (0-X). The width of the “output register” 2005 equals the number of columns X in the array (one bit per column) represented as In0 through InX. The number of “shift read register” commands 2002 required to read the entire array of elements is expressed as follows: (number of “fire counter” bits+number of charge/weight bits) times the number Y of elements per column in the array).

For example: If the fire counter 2003 is 16-bits and the charge/weight values are 8-bits and the array is a 100×100 element configuration (10,000 elements) then the number of “shift read register” commands 2002 required to read the array equals 24-bits/element times 100 or 2400 commands where Y equals 100.

The array state can be read while in full operation. The “load read register” command 2001 can either be triggered by the user interface, control program or by a firing event from the output elements of the array (the elements which are at the edge of the array and drive their fire events external to the array). The “fire counter” 2003 continues to maintain and track the number of fire events in an element even while the array is being read.

A software program may organize the data read from the array (Output 0-X of Output Register 2005) in a format representative of the structure and state of the DANNA array.

Referring now to FIG. 18, there is shown a network having a level-5 network of connections between selected elements, indicated by bold circles around those elements. If level-5 connectivity is desired for every element, then twenty-five such level-5 networks may be needed, each having connections to exactly one of the elements within the square indicated by the dashed lines.

Other levels of connections are possible; for example, Error! Reference source not found. illustrates a DANNA having a level-5 connection network, indicated by bold circles around those elements. If level-5 connectivity is desired for every element, then, 25 such level-5 networks are needed, each having connections to exactly one of the elements within the square indicated by the dashed lines. Note that although the shading is indicated for the elements of the level-2 networks, these connections are optional, as illustrated in FIG. 19, a DANNA illustrated with level-5 connections among six of the elements, as shown in FIG. 18, without the shading indicating the level-2 interconnection network and the possibility of 25 level-5 network of connections.

While the examples are illustrations of DANNA implementations having either one or all of the networks connecting elements at a given level, it should be understood that the designer may select which of these connection networks is to be implemented, choosing any subset or none at all. Furthermore, while the level-1 interconnection network, to each element's nearest neighbors, is necessary, all of the other levels are optional and are to be used at the discretion of the designer when implementing engine or process (such as an evolutionary optimization process or device). The utility of the additional levels of interconnection (potentially in a three dimensional space) to enable connectivity above and below the planes of the drawings shown in these figures is to enable signals (events) to be passed between elements that are not nearest neighbors more efficiently, and to overcome blockages of signal pathways due to the configuration of some elements of the DANNA. The multi-level interconnection networks corresponds to the concept of “rich club” neurons in biological tissue, where selected neurons can be utilized to transmit signals across long distances relative to the average inter-neuron distance. In a DANNA, these multi-level connection networks enable signals to be transmitted among elements at considerable distance across the array with minimal delays, offering additional flexibility in the design and configuration of the DANNA for a particular application such as in detection, classification, or control. The trade-off for this flexibility is the increased complexity of DANNA elements that incorporate multi-level signaling, where such complexity requires additional resources when implemented using a FPGA or with ASIC technology.

In conclusion, a dynamic and adaptive neural network array (DANNA) may use the NIDA neural network model proposed by Schuman/Birdwell in related patent application U.S. application Ser. No. 14/513,280, filed concurrently herewith, a programmable element design that can be configured to be a neuron or a synapse, and a 2-dimensional array structure and interface to allow neural networks to be created and dynamically modified. Synapse distance and LTP/LTD functions were also implemented. We have demonstrated the functionality, capacity and performance of this DANNA structure on Xilinx Virtex-7 FPGAs and project the maximum performance and capacity expected on Xilinx's largest FPGA. By moving the design to a custom VLSI design in the same CMOS process as the Xilinx FPGAs (28 nm), we believe we can increase capacities by two orders of magnitude (1 million elements) and network clocking rates by at least one order of magnitude (100 MHz). A NIDA/DANNA architecture can interface to the physical world (sensors, actuators, imaging devices, etc.) via ADCs, DACs, multiplexers and demultiplexers, other known interface technologies, or a combination of these technologies on its input and output elements, and the NIDA/DANNA array can be configured to perform selected tasks (detection, classification, pattern recognition, control, and image and video processing such as edge and feature detection, classification, and tracking). We have proven that a programmable neural network can be constructed using a simple array of elements built on an FPGA. The described embodiments apply this concept to real world problems such as control, anomaly detection and classification.

All United States and foreign patents and articles whose citations are provided above and below in the Bibliography should be deemed to be incorporated by reference as to their entire contents for the purposes of understanding the underlying technology behind an embodiment of a method and apparatus for constructing an artificial neural network in hardware or software according to the various embodiments of the several related patent applications. The embodiments of a method and apparatus for constructing a neuroscience-inspired artificial neural network architecture in the form of a DANNA array or a NIDA described above should only be deemed to be limited by the scope of the claims which follow.

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What we claim is:
 1. Apparatus for a neuromorphic network comprising an artificial neural network, the artificial neural network comprising a multi-dimensional array of interconnected circuit elements, each circuit element having similar components to one another selectively representing, under special purpose program control, one of a neuron and a synapse, at least one circuit element of the array selectively representing an input neuron, at least one circuit element of the array selectively representing an output synapse and under program control one to multiple circuit elements of the array selectively representing a neuron or a synapse connected between the input neuron and the output synapse.
 2. The apparatus of claim 1, the selected elements of the array comprising a programmable logic array, ASIC or VLSI component.
 3. The apparatus of claim 2, defined by a hardware description language, circuit diagram and/or logic equations.
 4. The apparatus of claim 3 wherein said hardware description language is one of VHDL and Verilog.
 5. The apparatus of claim 1 wherein at least one circuit element is a digital circuit element.
 6. The apparatus of claim 1 wherein at least one circuit element contains an analog electronic device.
 7. The apparatus of claim 6 wherein said analog electronic device is an analog signal storage device.
 8. The apparatus of claim 1, the special purpose program control implemented using one of a microprocessor, a microcontroller, and a processor core.
 9. The apparatus of claim 1 wherein a given circuit element representing a neuron is adapted to be connected to at least one destination neuron, each connection comprising at least one synapse, the connections resulting in an at least one level neural network structure.
 10. The apparatus of claim 1 wherein a circuit element of the array accepts greater than or equal to eight inputs in multiples of eight inputs.
 11. The apparatus of claim 1 wherein a circuit element of the array of interconnected circuit elements comprises an accumulator, a comparator, a refractory period input and a threshold input, the accumulator accumulating charge from a plurality of selectable inputs of the circuit element for comparison at the comparator with the threshold input, and, if the accumulated charge is greater than the threshold and if a refractory period has lapsed, the comparator causing a fire output of the circuit element.
 12. The apparatus of claim 1 wherein a circuit element of the array comprises a synapse distance/delay register having a synapse distance/delay input and a FIFO with sufficient entries to represent the maximum synapse distance/delay to hold input fire events, the synapse distance/delay register, responsive to an input fire multiplexer, outputting a fire signal to an element fire signal line according to the synapse distance/delay input.
 13. The apparatus of claim 1 wherein a plurality of circuit elements comprise neurons and synapses forming a loop, each synapse of the loop having a direction from a source neuron of the loop to a destination neuron of the loop around the loop.
 14. The apparatus of claim 13 wherein a second plurality of circuit elements comprise neurons and synapses, the second plurality of circuit elements forming a neural pathway sharing at least one neuron of the first plurality of neurons and synapses forming the loop.
 15. The apparatus of claim 1 further comprising an interface and control unit and a configuration unit for respectively interfacing with the array of neuron and synapse circuit elements and for configuring the array of neuron and synapse circuit elements under the special purpose program control of a controller and further comprising an interface to an external process to be controlled.
 16. The apparatus of claim 15, the controller further comprising an optimizing device for connection with the controller to the interface and control unit and the configuration unit.
 17. The apparatus of claim 16 further comprising one of a modulator and a demodulator for connection among the interface, control unit and an external process.
 18. The apparatus of claim 16 further comprising an optimization function implemented by the optimizing device and using input from a performance function, for measuring performance and modifying the artificial neural network to improve performance of one of a control, detection and classification application.
 19. The apparatus of claim 1 comprising it plurality of artificial neural networks, one artificial neural network, during a period of off-line learning, implementing a model of an external process comprising an application of the plurality of artificial neural networks, another artificial neural network of the plurality of artificial neural networks, during a period of on-line learning, reacting to events of the external process and a controller for judging performance of the at least one of the plurality of artificial neural networks from interactions with the external process, the model of the external process being modified by the controller as a result of said judged performance.
 20. The apparatus of claim 12 further comprising a clock circuit for generating a plurality of clock signals and an long-term potentiation and depression state machine, the clock signals comprising a network clock signal input to the synapse distance register and to a counter representing a long-term potentiation and depression refractory period signal, a long-term potentiation and depression refractory period signal to the long-term potentiation and depression state machine, the long-term potentiation and depression state machine for respectively outputting an increment/decrement weight signal to an accumulator of a circuit element representing a synapse.
 21. The apparatus of claim 1 wherein a given circuit element of the array connects to one of multiple circuit elements of the array m multiples of eight other circuit elements.
 22. The apparatus of claim 1 comprising an array of a plurality of X columns of circuit elements and Y rows of circuit elements, at least one circuit element being selectively enabled, each selectively enabled circuit element performing a selected function of one of a neuron and of a synapse, wherein X and Y are integers, the array having an output register for selectively receiving a value from a circuit element in a column and providing an output signal according to said received value.
 23. The apparatus of claim 1 comprising an array of a plurality of X columns of circuit elements and V rows of circuit elements, one circuit element representing a destination neuron and a plurality of connected circuit elements representing synapse circuit elements selectively connected under special purpose program control to the destination neuron such that long-term potentiation and depression occur symmetrically on synapses connected to enabled inputs of the destination neuron, the destination neuron's enabled input from the first output of a plurality of synapses being randomly sampled, and, thereafter, the plurality of synapses being sequentially sampled until all connected synapse inputs are sampled, the next input from a synapse to the destination neuron being randomly selected from the plurality of synapses.
 24. The apparatus of claim 23 wherein the array comprises the destination neuron connected to a plurality of synapses, one of the synapses emitting a weight signal on at least one of its outputs, the at least one output including an output of the weight signal to be received at an enabled input of the destination neuron, the destination neuron one of 1) having a charge state insufficient to fire upon receiving the weight signal, 2) being not refractory and having a charge state sufficient to fire and 3) being refractory, the connected synapse determining that its outputs caused the neuron to fire or did not cause the neuron to fire during a given clock cycle.
 25. The apparatus of claim 1 comprising an artificial neural network having at least one destination neuron and at least one connected synapse, each of the destination neuron and the synapse comprising one circuit element, the array having a network clock having a plurality of k cycles where k is an integer greater than zero network clock cycles, the at least one synapse being configured to implement a delay line of k greater than zero clock cycles and to emit a weight value causing the destination neuron to fire when the firing event is received at an enabled input of the destination neuron.
 26. The apparatus of claim 25 whereas the destination neuron continues to fire at least once every k, being greater than zero, clock cycles, the destination neuron and connected synapse forming an oscillating structure.
 27. The apparatus of claim 26 wherein the oscillating structure comprises a central pattern generator, the apparatus further comprising a database for storing at least a central pattern generator having at least one destination neuron and at least one connected synapse.
 28. The apparatus of claim 27, said artificial neural network comprising a central pattern generator being retrieved under program control from the database for a particular application of one of control, detection and classification.
 29. The apparatus of claim 1 comprising at least one artificial neural network determined using evolutionary optimization of firing parameters of neurons and delay parameters of synapses.
 30. A circuit element for use in a multi-dimensional artificial neural network array, the circuit element comprising a neuron/synapse select input for selecting one of a neuron and synapse function of the circuit element, an accumulator, a comparator, a refractory period input and a threshold input, the accumulator accumulating charge from a plurality of selectable inputs for comparison at the comparator with the threshold, and, if a refractory period has lapsed and the accumulated charge is greater than the threshold, the comparator causing a fire output of the circuit element of the neural network array when the circuit element selectively performs a neuron function.
 31. The circuit element of claim 30, the circuit element comprising a digital circuit element.
 32. The circuit element of claim 30 comprising a plurality of clock inputs to circuit elements, an accumulate clock input of the accumulator being one of the plurality of clock inputs, an acquire clock input and an input select signal to an input data multiplexer for inputting data to the accumulator and to an output tire component responsive 10 the comparator for outputting a fire signal, the acquire clock input being another of the plurality of clock inputs.
 33. The circuit element of claim 30 for selectively receiving a plurality of inputs at an input data multiplexer representing weight values, a weight value being received from at least one circuit element having a synapse function.
 34. The circuit element of claim 30 further comprising an input multiplexer for selectively receiving a plurality of inputs representing a fire signal received from at least one circuit element having a selected neuron function; and a long-term potentiation and depression state machine, responsive to the input multiplexer, for outputting an increment/decrement weight signal and for outputting a long-term potentiation and depression refractory period signal to a counter, the counter for receiving a control input representing a long-term potentiation and depression refractory period and enabling the increment/decrement weight signal.
 35. A method for constructing a neuromorphic network comprising at least one artificial neural network, the artificial neural network comprising a multi-dimensional array of interconnected circuit elements, each circuit element having similar components to one another selectively representing, under special purpose program control, one at a neuron and a synapse, at least one circuit element of the array selectively representing an input neuron, at least one circuit element of the array selectively representing an output synapse and under program control one to multiple circuit elements of the array selectively representing a neuron or a synapse connected between the input neuron and the output synapse.
 36. The method of claim 35 further comprising defining the special purpose program control by one of a hardware description language, a circuit diagram and logic equations.
 37. The method of claim 35 further comprising connecting a destination neuron to a plurality of synapses resulting in a multiple level neural network structural array of circuit elements.
 38. The method of claim 35, a circuit element of the array comprising an accumulator, a comparator, a refractory period input and it threshold input, the accumulator accumulating charge from a plurality of selectable inputs of the circuit element for comparison at the comparator with the threshold input, and, if the accumulated charge is greater than the threshold and if a refractory period has lapsed, the comparator causing a fire output of the circuit element.
 39. The method of claim 35, a circuit element of the array comprising a synapse distance register having a synapse distance input and a FIFO with sufficient entries to represent the maximum synapse distance to hold input fire events; the synapse distance register, responsive to an input fire multiplexer, outputting a fire signal to an element fire lead according to the synapse distance input.
 40. The method of claim 35, the array having an optimization device, the optimizing device measuring performance of the artificial neural network and modifying the artificial neural network for one of a control, detection and classification application to optimize performance of the application.
 41. The method of claim 35 wherein the artificial neural network comprises a plurality of artificial neural networks, the method further comprising, during a period of off-line learning, generating and improving a model of an external process comprising an application of one of the plurality of artificial neural networks, another artificial neural network of the plurality of artificial neural networks, during a period of on-line learning, reacting to events of the external process and judging performance of the one artificial neural network from interactions with the external process, the model of the external process being updated as the external process changes.
 42. The method of claim 35 wherein the array comprises the destination neuron connected to a plurality of synapses, one of the plurality of synapses emitting a weight signal on at least one of its outputs, the at least one output including an output of the weight signal to be received at an input of the destination neuron, the destination neuron one of 1) having a charge state insufficient to fire upon receiving the weight signal, 2) being not refractory and having a charge state sufficient to fire and 3) being refractory and adding the input weight to its charge state and not firing, the connected synapse determining that its outputs caused the neuron to fire or did not cause the neuron to fire during a given clock cycle.
 43. The method of claim 35 at least one artificial neural network for performing evolutionary optimization of a firing parameters of a neuron and a delay parameter of a synapse.
 44. A method for use in a circuit element of an artificial neural network, the circuit element having a neuron/synapse select input for selecting one of a neuron and synapse function of the Circuit element, an accumulator, a comparator, a refractory period input and a threshold input, the accumulator accumulating charge from a plurality of selectable inputs for comparison at the comparator with the threshold, and, if a refractory period has lapsed and the accumulated charge is greater than the threshold, the comparator causing a fire output of the circuit element when the circuit element selectively performs a neuron function.
 45. The method of claim 44, the circuit element further comprising an input multiplexer for selectively receiving a plurality of inputs representing a tire signal received from at least one circuit element having a selected neuron function and a long-term potentiation and depression state machine, responsive to the input multiplexer, the long-term potentiation and depression state machine outputting an increment/decrement weight signal and outputting a long-term potentiation and depression refractory period signal to a counter, the counter for receiving a control input representing a long-term potentiation and depression refractory period and enabling the increment/decrement weight signal. 